Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access

Abstract

Many promising interconnect materials have been proposed to replace traditional Copper interconnects. To enable a large design space exploration for various emerging interconnect technologies, we develop an efficient interconnect technology/memory co-design. In addition, we propose three H-tree technology options to minimize the H-tree delay and energy overheads of four interconnect materials and benchmark them against their traditional Cu counterparts. Various array-/subarray- and interconnect-level design parameters are co-designed for optimal system performance.