Browsing by author "Ervin, Joseph"
Now showing items 1-5 of 5
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CMOS area scaling and the need for high aspect ratio vias
Briggs, Basoene; Guissi, Sofiane; Wilson, Chris; Ryckaert, Julien; Paolillo, Sara; Vandersmissen, Kevin; Versluijs, Janko; Lorant, Christophe; Heylen, Nancy; Boemmels, Juergen; Tokei, Zsolt; Sherazi, Yasser; Weckx, Pieter; Kljucar, Luka; van der Veen, Marleen; Boccardi, Guillaume; De Heyn, Vincent; Gupta, Anshul; Ervin, Joseph; Kamon, Matt (2018) -
Evaluation of the impact of source/drain epi implementation on logic performance using combined process and circuit simulation
Soussou, Assawer; Schram, Tom; Miyaguchi, Kenichi; Chakarov, Ivan; Parvais, Bertrand; Ervin, Joseph (2020) -
Impact of EUV resist thickness on local critical dimension uniformities for sub-30 nm CD Via Patterning
Vincent, Benjamin; Maslow, Mask; Bekaert, Joost; Mao, Ming; Ervin, Joseph (2020) -
Self-aligned block and fully self-aligned via for iN5 metal 2 self-aligned quadruple patterning
Vincent, Benjamin; Franke, Joern-Holger; Juncker, Aurelie; Lazzarino, Frederic; Murdoch, Gayle; Halder, Sandip; Ervin, Joseph (2018) -
Self-aligned block and fully self-aligned via for iN5 Metal 2 Self-aligned quadruple patterning
Vincent, Benjamin; Franke, Joern-Holger; Juncker, Aurelie; Lazzarino, Frederic; Murdoch, Gayle; Halder, Sandip; Ervin, Joseph (2018)