Browsing by author "Papameletis, Christos"
Now showing items 1-19 of 19
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3D design-for-test architecture
Marinissen, Erik Jan; Konijnenburg, Mario; Verbree, Jouke; Chi, Chun-Chuan; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias; Shibin, Konstantin; Keller, Brion; Chickermane, Vivek; Goel, Sandeep K. (2019-03) -
A 3D-DfT demonstrator
Marinissen, Erik Jan; De Wachter, Bart; O'Loughlin, Stephen; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias (2014-05) -
A 3D-DfT demonstrator
Marinissen, Erik Jan; De Wachter, Bart; O'Loughlin, Stephen; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias (2014-06) -
A DfT architecture and tool flow for 3D-SICs with test data compression, embedded cores, and multiple towers
Papameletis, Christos; Keller, Brion; Chickermane, Vivek; Hamdioui, Said; Marinissen, Erik Jan (2015) -
At-Speed delay testing of inter-die connections of 2.5D- and 3D-SICs
Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-05) -
At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs
Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-05) -
At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs
Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-05) -
At-speed inter-die interconnect test in 2.5D- and 3D-SICs
Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-10) -
At-speed testing of inter-die connections of 3D-SICs in the presence of shore logic
Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-11) -
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers
Papameletis, Christos; Keller, Brion; Chickermane, Vivek; Marinissen, Erik Jan; Hamdioui, Said (2013) -
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers
Papameletis, Christos; Keller, Brion; Chickermane, Vivek; Marinissen, Erik Jan; Hamdioui, Said (2013-05) -
Design, test generation, processing, and pre- and post-bond measurement results of a 3D-DfT demonstrator chip stack
Marinissen, Erik Jan; De Wachter, Bart; O'Loughlin, Stephen; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias (2014-05) -
Design, test generation, processing, and pre- and post-bond measurement results of a 3D-DfT demonstrator chip stack
Marinissen, Erik Jan; De Wachter, Bart; O'Loughlin, Stephen; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias (2014) -
Embedded toggle generator to control the switching activity
Katselas, Leonidas; Athanasiadis, Angelos; Hatzopoulos, Alkis; Jiao, Hailong; Papameletis, Christos; Marinissen, Erik Jan (2017-09) -
Embedded toggle generator to provide realistic test conditions during test of digital 2D-SoCs and 3D-SICs
Katselas, Leonidas; Hatzopoulos, Alkis; Jiao, Hailong; Papameletis, Christos; Marinissen, Erik Jan (2018-05) -
Extension of a 3D-DfT architecture for embedded cores and multiple towers
Papameletis, Christos; Chickermane, Vivek; Keller, Brion; Marinissen, Erik Jan (2012) -
Imec's 3D-DfT architecture: basics, extensions, and demonstrator results
Marinissen, Erik Jan; De Wachter, Bart; O'Loughlin, Stephen; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias (2014-06) -
On-chip toggle generators to provide realistic conditions during test of digital 2D-SoCs and 3D-SICs
Katselas, Leonidas; Hatzopoulos, Alkis; Jiao, Hailong; Papameletis, Christos; Marinissen, Erik Jan (2018-11) -
Vesuvius-3D: A 3D-DfT demonstrator
Marinissen, Erik Jan; De Wachter, Bart; O'Loughlin, Stephen; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias (2014-10)