Browsing by author "Van der Plas, Geert"

10 and 7 mu m Pitch Thermo-compression Solder Joint, Using A Novel Solder Pillar And Metal Spacer Process

Derakhshandeh, Jaber; Capuz, Giovanni; Cherman, Vladimir; Inoue, Fumihiro; De Preter, Inge; Hou, Lin; Bex, Pieter; Gerets, Carine; Duval, Fabrice; Webers, Tomas; Bertheau, Julien; Van Huylenbroeck, Stefaan; Phommahaxay, Alain; Shafahian, Ehsan; Van der Plas, Geert; Beyne, Eric; Miller, Andy; Beyer, Gerald (2020)

3-D Integration from system design perspective

Milojevic, Dragomir; Van der Plas, Geert (2009)

3D chip package interaction thermo-mechanical challenges: proximity effects of through silicon vias and μ-bumps

Guo, Wei; Van der Plas, Geert; Ivankovic, Andrej; Eneman, Geert; Cherman, Vladimir; De Wachter, Bart; Mercha, Abdelkarim; Gonzalez, Mario; Civale, Yann; Redolfi, Augusto; Buisson, Thibault; Jourdain, Anne; Vandevelde, Bart; Rebibis, Kenneth June; De Wolf, Ingrid; La Manna, Antonio; Beyer, Gerald; Beyne, Eric; Swinnen, Bart (2012)

3D Heterogeneous Package Integration of Air/Magnetic Core Inductor: 89%-Efficiency Buck Converter with Backside Power Delivery Network

Sun, Xiao; Lin, Hesheng; Velenis, Dimitrios; Slabbekoorn, John; Talmelli, Giacomo; Bex, Pieter; Sterken, Tom; Lauwereins, Rudy; Adelmann, Christoph; Miller, Andy; Van der Plas, Geert; Beyne, Eric (2020)

3D heterogeneous system integration: Application driver for 3D technology development

Beyne, Eric; Marchal, Pol; Van der Plas, Geert (2011)

3D Integration: Circuit design, test and reliability challenges

Minas, Nikolaos; De Wolf, Ingrid; Marinissen, Erik Jan; Stucchi, Michele; Oprins, Herman; Mercha, Abdelkarim; Van der Plas, Geert; Velenis, Dimitrios; Marchal, Pol (2010)

3D SoC integration, beyond 2.5D chiplets

Beyne, Eric; Milojevic, Dragomir; Van der Plas, Geert; Beyer, Gerald (2021)

3D stacking induced mechanical stress effects

Cherman, Vladimir; Van der Plas, Geert; De Vos, Joeri; Ivankovic, Andrej; Lofrano, Melina; Simons, Veerle; Gonzalez, Mario; Vanstreels, Kris; Wang, Teng; Daily, Robert; Guo, Wei; Beyer, Gerald; La Manna, Antonio; De Wolf, Ingrid; Beyne, Eric (2014)

3D technology roadmap and status

Marchal, Pol; Van der Plas, Geert; Eneman, Geert; Moroz, V.; Badaroglu, Mustafa; Mercha, Abdelkarim; Thijs, Steven; Linten, Dimitri; Katti, Guruprasad; Stucchi, Michele; Vandevelde, Bart; Oprins, Herman; Cherman, Vladimir; Croes, Kris; Redolfi, Augusto; La Manna, Antonio; Travaly, Youssef; Beyne, Eric; Cartuyvels, Rudi (2011)

3D Wafer-to-Wafer Bonding Thermal Resistance Comparison: Hybrid Cu/dielectric Bonding versus Dielectric via-last Bonding

Oprins, Herman; Cherman, Vladimir; Webers, Tomas; Kim, Soon-Wook; de Vos, Joeri; Van der Plas, Geert; Beyne, Eric (2020)

3D-Integration: status, opportunities

Van der Plas, Geert; Marchal, Pol (2011)

3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes

Chen, Rongmei; Weckx, Pieter; Salahuddin, Shairfe Muhammad; Kim, Soon-Wook; Sisto, Giuliano; Van der Plas, Geert; Stucchi, Michele; Baert, Rogier; Debacker, Peter; Na, Myung Hee; Ryckaert, Julien; Milojevic, Dragomir; Beyne, Eric (2020)

3D-stacked integrated circuits: design consequences, architectural aspects, design methodologies and tools

Milojevic, Dragomir; Van der Plas, Geert (2009)

84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor

Lin, Hesheng; Velenis, Dimitrios; Nolmans, Philip; Sun, Xiao; Catthoor, Francky; Lauwereins, Rudy; Van der Plas, Geert; Beyne, Eric (2022)

91.5%-Efficiency fully integrated voltage regulator with 86fF/μm2-high-density 2.5 MIM capacitor

Lin, Hesheng; Velenis, Dimitrios; Nolmans, Philip; Sun, Xiao; Catthoor, Francky; Lauwereins, Rudy; Van der Plas, Geert; Beyne, Eric (2021)

A 0.65-to-1.4 nJ/burst 3-to-10 GHz UWB all-digital TX in 90 nm CMOS for IEEE 802.15.4a

Ryckaert, Julien; Van der Plas, Geert; De Heyn, Vincent; Desset, Claude; Van Poucke, Bart; Craninckx, Jan (2007)

A 0.65-to-1.4nJ/burst 3-to-10GHz UWB digital transmitter in 90nm CMOS for IEEE 802.15.4a

Ryckaert, Julien; Van der Plas, Geert; De Heyn, Vincent; Desset, Claude; Vanwijnsberghe, Geert; Van Poucke, Bart; Craninckx, Jan (2007-02)

A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC sigma-delta modulator in 1.2-V 90-nm CMOS

Morgado, Alonso; del Rio, Rocio; de la Rosa, Jose M.; Bos, Lynn; Ryckaert, Julien; Van der Plas, Geert (2010)

A 14 bit 130 MHz CMOS current-steering DAC with adjustable INL

Chen, Tao; Geens, Peter; Van der Plas, Geert; Dehaene, Wim; Gielen, Georges (2004-09)

A 150MS/s 133uW 7b ADC in 90nm digital CMOS using a comparator-based asynchronous binary search sub-ADC

Van der Plas, Geert; Verbruggen, Bob (2008-02)