Browsing by author "Wang, Hua"
Now showing items 1-12 of 12
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A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement
Wang, Hua; Papanikolaou, Antonis; Miranda, Miguel; Catthoor, Francky (2004) -
A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications
Papanikolaou, Antonis; Lobmaier, Florian; Wang, Hua; Miranda, Miguel; Catthoor, Francky (2005-09) -
A variability tolerant embedded SRAM offering runtime selectable energy/delay figures
Wang, Hua; Miranda Corbalan, Miguel; Geens, Peter; Dehaene, Wim; Catthoor, Francky (2007-05) -
Design and synthesis of Pareto buffers offering large range runtime energy/delay trade-offs via combined buffer size and supply voltage tuning
Wang, Hua; Miranda Corbalan, Miguel; Dehaene, Wim; Catthoor, Francky (2009) -
Impact of random soft oxide breakdown on SRAM energy/delay drift
Wang, Hua; Miranda Corbalan, Miguel; Catthoor, Francky; Dehaene, Wim (2007) -
Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design
Papanikolaou, Antonis; Wang, Hua; Miranda Corbalan, Miguel; Catthoor, Francky; Dehaene, Wim (2008) -
Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design
Papanikolaou, Antonis; Wang, Hua; Miranda Corbalan, Miguel; Catthoor, Francky (2007-07) -
Sub-THz and THz signal generation using photonic and electronic techniques
Banerjee, Aritra; Zhang, Lei; Wang, Hua; Wambacq, Piet (2019) -
Synthesis of runtime switchable pareto buffers offering full range fine grained energy/delay trade-offs
Wang, Hua; Catthoor, Francky; Miranda Corbalan, Miguel; Dehaene, Wim (2008) -
Systematic analysis of energy and delay impact of very deep submicron process variability effects in embedded SRAM modules
Wang, Hua; Miranda, Miguel; Dehaene, Wim; Catthoor, Francky; Maex, Karen (2005-03) -
Variable tapered pareto buffer design and implementation allowing run-time configuration for low power embedded SRAMs
Wang, Hua; Miranda, Miguel; Papanikolaou, Antonis; Catthoor, Francky; Dehaene, Wim (2005-10)