Browsing by author "Zografos, Odysseas"
Now showing items 1-20 of 54
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A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes
Nibhanupudi, S. S. Teja; Prasad, Divya; Das, Shidhartha; Zografos, Odysseas; Robinson, Alex; Gupta, Anshul; Spessot, Alessio; Debacker, Peter; Verkest, Diederik; Ryckaert, Julien; Hellings, Geert; Myers, James; Cline, Brian; Kulkarni, Jaydeep P. (2022-07-07) -
A Novel System-Level Physics-based Electromigration Modelling Framework: Application to the Power Delivery Network
Zahedmanesh, Houman; Ciofi, Ivan; Zografos, Odysseas; Badaroglu, Mustafa; Croes, Kristof (2021) -
Area and routing efficiency of SWD circuits compared to advanced CMOS
Zografos, Odysseas; Raghavan, Praveen; Sherazi, Yasser; Vaysset, Adrien; Ciubotaru, Florin; Soree, Bart; Lauwereins, Rudy; Radu, Iuliana; Thean, Aaron (2015) -
Buried power rails and back-side power grids: ARM CPU power delivery network design beyond 5nm
Prasad, D.; Nibhanupudi, S.; Das, S.; Zografos, Odysseas; Chehab, Bilal; Sarkar, Satadru; Baert, Rogier; Robinson, A.; Gupta, Anshul; Spessot, Alessio; Debacker, Peter; Verkest, Diederik; Kulkarni, J.; Cline, B.; Sinha, S. (2019) -
Chain of magnetic tunnel junctions as a spintronic memristor
Raymenants, Eline; Vaysset, Adrien; Wan, Danny; Manfrini, Mauricio; Zografos, Odysseas; Bultynck, Olivier; Doevenspeck, Jonas; Heyns, Marc; Radu, Iuliana; Devolder, Thibaut (2018) -
Confined magnetoelastic waves in thin waveguides
Vanderveken, Frederic; Mulkers, Jeroen; Leliaert, Jonathan; Van Waeyenberge, Bartel; Soree, Bart; Zografos, Odysseas; Ciubotaru, Florin; Adelmann, Christoph (2021) -
Confined magnetoelastic waves in thin waveguides
Vanderveken, Frederic; Mulkers, Jeroen; Leliaert, Jonathan; Van Waeyenberge, Bartel; Soree, Bart; Zografos, Odysseas; Ciubotaru, Florin; Adelmann, Christoph (2021) -
Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS
Zografos, Odysseas; Soree, Bart; Vaysset, Adrien; Cosemans, Stefan; Amaru, Luca; Gaillardon, Pierre-Emmanuel; De Micheli, Giovanni; Lauwereins, Rudy; Sayan, Safak; Raghavan, Praveen; Radu, Iuliana; Thean, Aaron (2015) -
Design and simulation of plasmonic interference-based majority gate
Doevenspeck, Jonas; Zografos, Odysseas; Gurunarayanan, Surya; Lauwereins, Rudy; Raghavan, Praveen; Soree, Bart (2017) -
Design enablement of CFET devices for sub-2nm CMOS nodes
Zografos, Odysseas; Chehab, Bilal; Schuddinck, Pieter; Mirabelli, Gioele; Kakarla, Naveen; Xiang, Yang; Weckx, Pieter; Ryckaert, Julien (2022-05-19) -
Device-, circuit- & block-level evaluation of CFET in a 4 track library
Schuddinck, Pieter; Zografos, Odysseas; Weckx, Pieter; Matagne, Philippe; Sarkar, Satadru; Sherazi, Yasser; Baert, Rogier; Jang, Doyoung; Yakimets, Dmitry; Gupta, Anshul; Parvais, Bertrand; Ryckaert, Julien; Verkest, Diederik; Mocuta, Anda (2019) -
Disruptive Technology Elements, and Rapid and Accurate Block-Level Performance Evaluation for 3nm and Beyond
Na, Myung Hee; Jang, Doyoung; Baert, Rogier; Sarkar, Satadru; Patli, Sudhir; Zografos, Odysseas; Chehab, Bilal; Spessot, Alessio; Sisto, Giuliano; Schuddinck, Pieter; Mertens, Hans; Oniki, Yusuke; Hellings, Geert; Dentoni Litta, Eugenio; Ryckaert, Julien; Horiguchi, Naoto (2021) -
Enabling sub-5nm CMOS technology scaling thinner and taller!
Ryckaert, Julien; Na, Myung Hee; Weckx, Pieter; Jang, Doyoung; Schuddinck, Pieter; Chehab, Bilal; Patli, Sudhir; Sarkar, Satadru; Zografos, Odysseas; Baert, Rogier; Verkest, Diederik (2019) -
ESD characterization of high mobility SiGe quantum well and Ge devices for future CMOS scaling
Hellings, Geert; Linten, Dimitri; Thijs, Steven; Chen, Shih-Hung; Witters, Liesbeth; Mitard, Jerome; Zografos, Odysseas; Groeseneken, Guido (2012) -
ESD performance of high mobility SiGe quantum well bulk FinFET diodes and pMOS devices
Linten, Dimitri; Hellings, Geert; Zografos, Odysseas; Chen, Shih-Hung; Scholz, Mirko; Veloso, Anabela; Groeseneken, Guido (2013) -
Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3 nm Era
Sisto, Giuliano; Zografos, Odysseas; Chehab, Bilal; Kakarla, Naveen; Xiang, Yang; Milojevic, Dragomir; Weckx, Pieter; Hellings, Geert; Ryckaert, Julien (2022) -
Exact synthesis for logic synthesis applications with complex constraints
Testa, Eleonora; Soeken, Matthias; Zografos, Odysseas; Catthoor, Francky; De Micheli, Giovanni (2017) -
Exchange-driven magnetic logic
Zografos, Odysseas; Manfrini, Mauricio; Vaysset, Adrien; Soree, Bart; Ciubotaru, Florin; Adelmann, Christoph; Lauwereins, Rudy; Raghavan, Praveen; Radu, Iuliana (2017-09) -
Extended Scale Length Theory Targeting Low-Dimensional FETs for Carbon Nanotube FET Digital Logic Design-Technology Co-optimization
Gilardi, C.; Chehab, Bilal; Sisto, Giuliano; Schuddinck, Pieter; Ahmed, Zuhaib; Zografos, Odysseas; Lin, Q.; Hellings, Geert; Ryckaert, Julien; Wong, H-S P.; Mitra, S. (2021) -
Fast characterization of input-output behavior of non-charge-based logic devices by machine learning
Kaintura, A.; Foss, K.; Zografos, Odysseas; Couckuyt, Ivo; Vaysset, A.; Dhaene, Tom; Soree, Bart (2020-08)