Browsing by author "Kernstock, C."
Now showing items 1-6 of 6
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A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics
Schanovsky, F.; Rzepa, G.; Stanojevic, Z.; Kernstock, C.; Baumgartner, O.; Karner, M.; Verreck, Devin; Arreghini, Antonio; Rosmeulen, Maarten (2021) -
Monolithic TCAD simulation of phase-change memory (PCM/PRAM) plus Ovonic Threshold Switch (OTS) selector device
Thesberg, M.; Stanojevic, Z.; Baumgartner, O.; Kernstock, C.; Leonelli, D.; Barci, M.; Wang, X.; Zhou, X.; Jiao, H.; Donadio, Gabriele Luca; Garbin, Daniele; Witters, Thomas; Kundu, Shreya; Hody, Hubert; Delhougne, Romain; Kar, Gouri Sankar; Karner, M. (2023) -
Physical modeling of NBTI: from individual defects to devices
Rzepa, G.; Goes, W.; Rott, G.; Rott, K.; Karner, M.; Kernstock, C.; Kaczer, Ben; Reisinger, H.; Grasser, T. (2014) -
Quantitative 3-D model to explain large single trap charge variability in vertical NAND memory
Verreck, Devin; Arreghini, Antonio; Bastos, Joao; Schanovsky, Franz; Mitterbauer, Ferdinand; Kernstock, C.; Karner, Markus; Degraeve, Robin; Van den Bosch, Geert; Furnemont, Arnaud (2019) -
Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies
Rzepa, G.; Karner, M.; Baumgartner, O.; Strof, G.; Schanovsky, F.; Mitterbauer, F.; Kernstock, C.; Karner, H. W.; Stanojevic, Z.; Weckx, Pieter; Hellings, Geert; Claes, Dieter; Wu, Zhicheng; Xiang, Yang; Chiarella, Thomas; Parvais, Bertrand; Mitard, Jerome; Franco, Jacopo; Kaczer, Ben; Linten, Dimitri (2021) -
Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling
Verreck, Devin; Arreghini, Antonio; Schanovsky, F.; Rzepa, G.; Stanojevic, Z.; Mitterbauer, F.; Kernstock, C.; Baumgartner, O.; Karner, M.; Van den Bosch, Geert; Rosmeulen, Maarten (2021)