Browsing by author "Yin, K.M."

Now showing items 1-4 of 4

    • Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack 

      Veloso, Anabela; Yu, HongYu; Lauwers, Anne; Chang, Shou-Zen; Adelmann, Christoph; Onsia, Bart; Demand, Marc; Brus, Stephan; Vrancken, Christa; Singanamalla, Raghunath; Lehnen, Peer; Kittl, Jorge; Kauerauf, Thomas; Vos, Rita; O'Sullivan, Barry; Van Elshocht, Sven; Mitsuhashi, Riichirou; Whittemore, G.; Yin, K.M.; Niwa, Masaaki; Hoffmann, Thomas; Absil, Philippe; Jurczak, Gosia; Biesemans, Serge (2007-09)

    • Achieving low-VT Ni-FUSI CMOS via Lanthanide incorporation in the gate stack 

      Veloso, Anabela; Yu, HongYu; Lauwers, Anne; Chang, Shou-Zen; Adelmann, Christoph; Onsia, Bart; Demand, Marc; Brus, Stephan; Vrancken, Christa; Singanamalla, Raghunath; Lehnen, Peer; Kittl, Jorge; Kauerauf, Thomas; Vos, Rita; O'Sullivan, Barry; Van Elshocht, Sven; Mitsuhashi, Riichirou; Whittemore, G.; Yin, K.M.; Niwa, Masaaki; Hoffmann, Thomas; Absil, Philippe; Jurczak, Gosia; Biesemans, Serge (2008)

    • Demonstration of metal-gated low Vt n-MOSFETs using a Poly-Si/TaN/Dy2O3/SiON gate stack with a scaled EOT value 

      Yu, HongYu; Singanamalla, Raghunath; Ragnarsson, Lars-Ake; Chang, Vincent; Cho, Hag-Ju; Mitsuhashi, Riichirou; Adelmann, Christoph; Van Elshocht, Sven; Lehnen, Peer; Chang, Shou-Zen; Yin, K.M.; Schram, Tom; Kubicek, Stefan; De Gendt, Stefan; Absil, Philippe; De Meyer, Kristin; Biesemans, Serge (2007)

    • Low Vt Ni-FUSI CMOS technology using a DyO cap layer with either single or dual Ni-phases 

      Yu, HongYu; Chang, Shou-Zen; Veloso, Anabela; Lauwers, Anne; Adelmann, Christoph; Onsia, Bart; Van Elshocht, Sven; Singanamalla, Raghunath; Demand, Marc; Vos, Rita; Kauerauf, Thomas; Brus, Stephan; Shi, Xiaoping; Kubicek, Stefan; Vrancken, Christa; Mitsuhashi, Riichirou; Lehnen, Peer; Kittl, Jorge; Niwa, M.; Yin, K.M.; Hoffmann, Thomas; De Gendt, Stefan; Jurczak, Gosia; Absil, Philippe; Biesemans, Serge (2007)