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Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs
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Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs
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Date
2016
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Huynh Bao, Trong
;
Ryckaert, Julien
;
Sakhare, Sushil
;
Mercha, Abdelkarim
;
Verkest, Diederik
;
Thean, Aaron
;
Wambacq, Piet
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2568
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Acq. date: 2025-12-15
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Metrics
Views
2568
since deposited on 2021-10-23
2
last month
Acq. date: 2025-12-15
Citations