Publication:

Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

Date

2016
Proceedings Paper
Simple item page Full metadata Statistics
 
dc.contributor.authorHuynh Bao, Trong
dc.contributor.authorRyckaert, Julien
dc.contributor.authorSakhare, Sushil
dc.contributor.authorMercha, Abdelkarim
dc.contributor.authorVerkest, Diederik
dc.contributor.authorThean, Aaron
dc.contributor.authorWambacq, Piet
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorMercha, Abdelkarim
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorThean, Aaron
dc.contributor.imecauthorWambacq, Piet
dc.contributor.orcidimecMercha, Abdelkarim::0000-0002-2174-6958
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.date.accessioned2021-10-23T11:26:21Z
dc.date.available2021-10-23T11:26:21Z
dc.date.issued2016
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/26760
dc.identifier.urlhttp://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=2505310
dc.source.beginpage978102
dc.source.conferenceDesign-Process-Technology Co-optimization for Manufacturability X
dc.source.conferencedate21/02/2016
dc.source.conferencelocationSan Jose, CA USA
dc.title

Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

dc.typeProceedings paper
dspace.entity.typePublication
Files
Publication available in collections:
Conference contributions