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Publication:

A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS

Date

2014

Proceedings Paper

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Files

30136.pdf 367.78 KB

Author(s)

Spagnolo, Annachiara

;

Verbruggen, Bob

;

D'amico, Stefano

;

Statistics

2006 since deposited on 2021-10-22

Acq. date: 2026-07-28