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Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs
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Authors
Huynh Bao, Trong
;
Ryckaert, Julien
;
Sakhare, Sushil
;
Mercha, Abdelkarim
;
Verkest, Diederik
;
Thean, Aaron
;
Wambacq, Piet
Conference
Design-Process-Technology Co-optimization for Manufacturability X
Title
Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs
Publication type
Proceedings paper
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