Browsing by Author "Agarwal, Rahul"
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Publication Cu/Sn microbumps interconnect for 3D TSV chip stacking
Proceedings paper2010, IEEE 60th Electronic Components and Technology Conference - ECTC, 1/06/2010, p.858-863Publication Design issues and cosiderations for low-cost 3D TSV IC technology
Proceedings paper2010, IEEE International Solid-State Circuits Conference - ISSCC, 8/02/2010, p.148-149Publication Diamond bit cutting for processing high topography wafers
Proceedings paper2009, 11th Electronics Packaging Technology Conference - EPTC, 9/12/1990Publication Die stacking using 3D-wafer level packaging copper/polymer through-Si via technology and Cu/Sn interconnect bumping
Proceedings paper2009, IEEE International Conference on 3D System Integration, 28/09/2009Publication Enabling 10μm pitch hybrid Cu-Cu IC stacking with Through Silicon Vias
Proceedings paper2010, IEEE 60th Electronic Components and Technology Conference - ECTC, 1/06/2010, p.1083-1087Publication High density Cu-Sn TLP bonding for 3D integration
Proceedings paper2009, 59th Electronic Components and Technology Conference - ECTC, 26/05/2009, p.345-349Publication Insertion bonding: A novel Cu-Cu bonding approach for 3D integration
Proceedings paper2010, IEEE 60th Electronics Components and Technology Conference - ECTC, 1/06/2010, p.1370-1375Publication Low temperature direct Cu-Cu immersion bonding for 3D integration
Publication Novel Cu-Cu bonding technique: the insertion bonding approach
Journal article2011, IEEE Transactions on Components, Packaging and Manufacturing Technology, (1) 12, p.1885-1894Publication Surface planarization of Cu/Sn micro-bump and its application in fine pitch Cu/Sn solid state diffusion bonding
Proceedings paper2010, 12th Electronics Packaging Technology Conference - EPTC, 8/12/2010, p.143-146Publication Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack – challenges and solutions
Proceedings paper2010-09, IEEE Custom Integrated Circuits Conference - CICC, 19/09/2010, p.1-4