Browsing by Author "Agopian, Paula G. D."
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Publication Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures
Journal article2021, IEEE TRANSACTIONS ON ELECTRON DEVICES, (68) 7, p.3630-3635Publication Analysis of the ZTC-Point for Vertically Stacked Nanosheet pMOS Devices
Proceedings paper2021, Latin America Electron Devices Conference (LAEDC), APR 19-21, 2021Publication Analysis of zero-temperature coefficient behavior on vertically stacked double nanosheet nMOS devices
Journal article2021, MICROELECTRONICS JOURNAL, 117, p.105277Publication Design of operational transconductance amplifier with Gate-All-Around Nanosheet MOSFET using experimental data from room temperature to 200 degrees C
Journal article2022, SOLID-STATE ELECTRONICS, (189) March, p.108238Publication Experimental Analysis of Trade-Off Between Transistor Efficiency and Unit Gain Frequency of Nanosheet NMOS Transistors
Proceedings paper2021, 35th Symposium on Microelectronics Technology and Devices (SBMicro), AUG 23-27, 2021Publication Experimental comparison between pMuGTFET and pFinFET analog performance as a function of temperature
Journal article2013, IEEE Transactions on Electron Devices, (60) 8, p.2493-2497Publication Experimental study of MISHEMT from 450 K down to 200 K for analog applications
Journal article2023, SOLID-STATE ELECTRONICS, (208) October, p.Art. 108742Publication High Temperature Influence on the Trade-off between gm/I-D and f(T) of nanosheet NMOS Transistors with Different Metal Gate Stack
Proceedings paper2021, Joint International EUROSOI Workshop / International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), SEP 01-03, 2021Publication Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs
Journal article2021, SOLID-STATE ELECTRONICS, 186, p.108099Publication Influence of the Ge amount at the source on transistor efficiency of vertical gate all around TFETs for different conduction regimes
;Mendes Bordallo, Ciao Cesar ;Sivieri, Victor B. ;Martino, Joao AntonioAgopian, Paula G. D.Proceedings paper2016, Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon -ULIS, 25/01/2016, p.P23Publication Low frequency noise analysis and modeling in vertical tunnel FETs with Ge Source
;Neves, Felipe ;Agopian, Paula G. D. ;Martino, Joao A. ;Cretu, BogdanRooyackers, RitaJournal article2016, IEEE Transactions on Electron Devices, (63) 4, p.1658-1665Publication Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approach
Proceedings paper2021, Joint International EUROSOI Workshop / International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), SEP 01-03, 2021Publication Operational Transconductance Amplifier Designed with SiGe-source Nanowire Tunnel-FET using Experimental Lookup Table Model
Proceedings paper2020, Joint International EUROSOI Workshop / International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), SEP 01-30, 2020Publication Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K
Proceedings paper2023, 37th Symposium on Microelectronics Technology and Devices (SBMicro), AUG 28-SEP 01, 2023Publication Temperature influence on experimental analog behavior of MISHEMTs
Journal article2025, SOLID-STATE ELECTRONICS, (223) January, p.Art. 109028Publication Trade-off analysis between gm/I-D and f(T) of nanosheet NMOS transistors with different metal gate stack at high temperature
Journal article2022, SOLID-STATE ELECTRONICS, 191, p.108267Publication Two-Stage Transconductance Operational Amplifier designed with VFET experimental data
Proceedings paper2024, 38th Symposium on Microelectronics Technology and Devices (SBMicro), SEP 02-06, 2024