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Browsing by Author "Buisson, Thibault"

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    300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications

    Jourdain, Anne  
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    Buisson, Thibault
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    Phommahaxay, Alain  
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    Privett, Marc
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    Wallace, Daniel
    Meeting abstract
    2010-11, IEEE International 3D System Integration Conference - 3DIC, 16/11/2010
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    3D chip package interaction thermo-mechanical challenges: proximity effects of through silicon vias and μ-bumps

    Guo, Wei  
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    Van der Plas, Geert  
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    Ivankovic, Andrej
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    Eneman, Geert  
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    Cherman, Vladimir  
    Proceedings paper
    2012, IEEE International Conference on IC Design and technology - ICICDT, 30/05/2012
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    3D integration challenges for fine pitch back side micro-bumping on ZoneBOND™ wafers

    Buisson, Thibault
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    De Preter, Inge  
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    Suhard, Samuel  
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    Vandersmissen, Kevin  
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    Jaenen, Patrick  
    Proceedings paper
    2012, 4th Electronics System Integration Technologies Conference - ESTC, 17/09/2012
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    3D stacking using ultra thin dies

    La Manna, Antonio  
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    Velenis, Dimitrios  
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    Buisson, Thibault
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    Detalle, Mikael  
    Proceedings paper
    2012, IEEE International 3D System Integration Conference - 3DIC, 31/01/2012, p.3-Mar
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    An IC-centric biocompatible chip encapsulation fabrication process

    Op de Beeck, Maaike  
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    La Manna, Antonio  
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    Buisson, Thibault
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    Dy, Eric
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    Velenis, Dimitrios  
    Proceedings paper
    2010, Electronics System Integratio Technology Conference - ESTC, 13/09/2010
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    Analysis of microbump induced stress effects in 3D stacked IC technologies

    Ivankovic, Andrej
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    Van der Plas, Geert  
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    Moroz, V.
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    Choi, M.
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    Cherman, Vladimir  
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    Mercha, Abdelkarim  
    Proceedings paper
    2012, IEEE International 3D System Integration Conference - 3DIC, 31/01/2012, p.9-Apr
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    Challenges and improvements for 3D-IC integration using ultra thin (25μm) devices

    La Manna, Antonio  
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    Buisson, Thibault
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    Detalle, Mikael  
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    Rebibis, Kenneth June  
    Proceedings paper
    2012-06, 62nd Electronic Components and Technology Conference - ECTC, 29/05/2012, p.532-536
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    Development of integrated wet cleans for 3D-SIC technologies

    Suhard, Samuel  
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    Simms, Ihsan
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    Brown, Ian
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    Shogo, Mizota
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    Koji, Kagawa
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    Claes, Martine  
    Proceedings paper
    2013, Ultra Clean Processing of Semiconductor Surfaces XI - UCPSS, 17/09/2012, p.150-153
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    Dry etch solutions for 3D integration technology

    Tutunjyan, Nina  
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    Van Cauwenberghe, Marc  
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    Verdonck, Patrick  
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    Majeed, Bivragh  
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    Buisson, Thibault
    Meeting abstract
    2010, 3rd Plasma Etch and Strip in Microelectronics Workshop - PESM, 4/03/2010
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    Integration challenges of Cu pillars with extreme wafer thinning for 3D stacking and packaging

    Buisson, Thibault
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    Potoms, Goedele  
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    Phommahaxay, Alain  
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    Verbinnen, Greet  
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    Jaenen, Patrick  
    Proceedings paper
    2011, 13th Electronics Packaging Technology Conference - EPTC, 7/12/2011
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    Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications

    Jourdain, Anne  
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    Buisson, Thibault
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    Phommahaxay, Alain  
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    Redolfi, Augusto  
    Proceedings paper
    2011, IEEE 61st Electronic Components and Technology Conference - ECTC, 31/05/2011, p.1122-1125
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    Key elements for sub-50μm pitch micro bump processes

    De Vos, Joeri  
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    Bogaerts, Lieve  
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    Buisson, Thibault
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    Gerets, Carine  
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    Jamieson, Geraldine  
    Proceedings paper
    2013, 63rd Electronic Components and Technology Conference - ECTC, 28/05/2013, p.1122-1126
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    Ultra thin chip embedding technology (UTCS-UTCP)

    Beyne, Eric  
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    Christiaens, Wim
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    Torfs, Tom  
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    Huwel, W.
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    Perdu, Wim
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    Vanfleteren, Jan  
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    Iker, Francois
    Oral presentation
    2010, Embedded Wafer level Packaging Workshop, IMAPS-France
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    Ultra thin die embedding technology with 20um-pitch interconnection

    Funaya, Takuo
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    Buisson, Thibault
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    De Preter, Inge  
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    Beyne, Eric  
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    Iker, Francois
    Proceedings paper
    2010, IEEE 60th Electronic Components and Technology Conference - ECTC, 1/06/2010, p.1575-1580
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    Wafer thinning and back side processing to enable 3D stacking

    Detalle, Mikael  
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    Bogaerts, Lieve  
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    La Manna, Antonio  
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    Buisson, Thibault
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    Velenis, Dimitrios  
    Proceedings paper
    2012, 4th Electronics System Integration Technologies Conference - ESTC, 17/09/2012

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