Browsing by Author "Chen, Shih-Hung"

A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOl CMOS with +15dBm IIP3 and >1kV HBM ESD protection

A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology

A 28 GHz front-end module with T/R switch achieving 17.2 dBm P-sat, 21.5% PAE(max) and 3.2 dB NF in 22 nm FD-SOI for 5G communication

Active-lite interposer for 2.5 & 3D integration

Advanced CMOS Technology Challenges for Robust ESD Design

An insight into the effects induced by heavy-ion strikes in

Bidirectional NPN ESD protection in silicon photonics technology

Calibration and modeling of LICCDM setups

CDM ESD testing of a 3D TSV stacked IC chip

CDM protection of a 3D TSV memory IC with a 100 GB/s Wide I/O data bus

CDM-time domain turn-on transient of ESD diodes in bulk FinFET and GAA NW technologies

Challenges and solutions for ESD protection in advanced logic and RF CMOS technologies

Challenges for ESD solutions in germanium-based technologies

Challenges for I/O towards the 3-nm node: Si/SiGe superlatttice I/O finFET in a horizontal nanowire technology and the increased ausceptibility of bulk finFET technology to single event latchup

Charged device model (CDM) ESD challenges for laterally diffused nMOS (nLDMOS) silicon controlled rectifier (SCR) devices for high-voltage applications in standard low-voltage CMOS technology

Comparison of system-level ESD design methodologies – towards the efficient and ESD robust design of systems

Comprehensive Investigations of HBM ESD Robustness for GaN-on-Si RF HEMTs

Concise analytical expression for Wunsch-Bell 1-D pulsed heating and applications in ESD using TLP

Defect characterization after ESD stress: merging TLP and Pulsed-IV techniques

Design and Analysis of a 28 GHz T/R Front-End Module in 22-nm FD-SOI CMOS Technology