Browsing by Author "Cotrin Teixeira, Ricardo"
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Publication 3D Embedding and interconnection of ultra thin (<20um) silicon dies
Proceedings paper2007, 9th Electronics Packaging Technology Conference - EPTC, 10/12/2007, p.222-226Publication 3D stacked IC demonstration using a through silicon via first approach
Proceedings paper2008, Technical Digest International Electron Devices Meeting - IEDM, 15/12/2008, p.603-606Publication Diamond bit cutting as alternative to polymer patterning for 3D interconnections technologies
Proceedings paper2009, 59th Electronic Components and Technology Conference - ECTC, 26/05/2009, p.1284-1288Publication Diamond bit cutting for processing high topography wafers
Proceedings paper2009, 11th Electronics Packaging Technology Conference - EPTC, 9/12/1990Publication Die level thinning down to 15μm thickness
; ; ; Publication High density 3D die stacking without through-Si-vias: ultra thin chip embedding as enabling technology
Proceedings paper2008, SEMICON Europe: Advanced Packaging Conference, 7/10/2008Publication Impact of thinning and packaging on a deep sub-micron CMOS product
; Yang, YuOral presentation2009, Design, Automation & Test in Europe Conference -DATE : Workshop on 3D Integration (W5)Publication Process induced sub-surface damage in mechanically ground silicon wafers
; ; Publication Statistical analysis of the influence of thinning processes on the strength of silicon
Proceedings paper2009, Materials Technology for 3-D Integration, 1/12/2008, p.1112-E03-09Publication Stress analysis on ultra thin ground wafers
; ; ; Journal article2008, Journal of Integrated Circuits and Systems, (3) 2, p.83-89Publication Stress analysis on ultra thin ground wafers
; ; ; Proceedings paper2007-09, Microelectronics Technology and Devices - SBMICRO, 3/09/2007, p.113-121Publication The influence of grinding and cleaning on Deep Reactive Ion Etching
Meeting abstract2009, 2nd International PESM Workshop on Plasma Etch and Strip in Microelectronics - PESM, 26/02/2009Publication Thickness characterization of ultra thin wafers on carrier
Proceedings paper2007-12, 9th Electronics Packaging Technology Conference - EPTC, 10/12/2007, p.238-241Publication Wafer thinning and planarization tech-nology for 3D Interconnects
Proceedings paper2008, 13th International C.M.P. Planarization for ULSI Multilevel Interconnection Conference - CMP-MIC, 3/03/2008