Browsing by Author "Goel, Sandeep K."

3D design-for-test architecture

Automated design-for-test for 2.5D and 3D SICs

Automation of 3D DfT insertion and interconnect test generation

Automation of 3D-DfT insertion

Automation of 3D-DfT insertion

DfT architecture and ATPG for interconnect tests of JEDEC wide-IO memory-on-logic die stacks

DfT insertion and interconnect test generation for 3D stacks with JEDEC wide-IO DRAM

IEEE Std P1838: 3D test access standard under development

Multi-visit TAMs to reduce the post-bond test length of 2.5D-SICs with a passive silicon interposer base

Test and debug strategy for TSMC CoWoS stacking process-based heterogeneous 3D-IC: A silicon study

Test-architecture optimization and test scheduling for TSV-based 3D stacked ICs

Testing of SOCs with hierarchical cores: common fallacies, test-access optimization, and test scheduling