Browsing by Author "Nagata, Makoto"
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Publication A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring
Proceedings paper2014, Electronics System-Integration Technology Conference - ESTC, 16/09/2014, p.1-5Publication A study on substrate noise coupling among TSVs in 3D chip stack
Journal article2018, IEICE Electronics Express, (15) 13, p.20180460Publication Broadband metal-insulator-metal capacitors on silicon interposer for low impedance power distribution network
Meeting abstract2015, DATE Workshop: 3D Integration Technology, Architecture, Design, Package, Automation, and Test, 13/03/2015Publication CDM protection of a 3D TSV memory IC with a 100 GB/s Wide I/O data bus
Proceedings paper2014-09, EOS/ESD Symposium Proceedings, 7/09/2014, p.61-67Publication In-tier diagnosis of power domains in 3D TSV ICs
Proceedings paper2012, IEEE International 3D Systems Integration Conference - 3DIC, 31/01/2012, p.7-FebPublication Measurements and analysis of substrate noise coupling in TSV based 3D integrated circuits
; ; Journal article2014-06, IEEE Transactions on Components, Packaging and Manufacturing Technology, (4) 6, p.1026-1037Publication Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements
Journal article2022, IEEE DESIGN & TEST, (39) 5, p.79-87Publication Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring
Proceedings paper2021, 26th IEEE European Test Symposium (ETS), MAY 24-28, 2021