Browsing by Author "Patel, Jash"
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Publication Comparison between wet and dry silicon via reveal in 3D backside processing
Proceedings paper2015, 12th Annual International Wafer Level Packaging Workshop - IWLPC, 13/10/2015Publication Demonstration of a collective hybrid die-to-wafer integration using glass carrier
Proceedings paper2021, IEEE 71st Electronic Components and Technology Conference (ECTC), JUN 01-JUL 04, 2021, p.2064-2070Publication Extreme thinning of Si wafers for via-last and multi wafer stacking applications
Proceedings paper2018, IEEE 68th Electronic Components and Technology Conference - ECTC, 29/05/2018, p.1-8Publication Extreme wafer thinning optimization for via-last applications
; ; ; ; ; Proceedings paper2016, IEEE International Conference on 3D System Integration - 3DIC, 8/11/2016, p.1-4Publication Impact of backside processing on C-V characteristics of TSV capacitors in 3D stacked IC process flows
Proceedings paper2015, 17th Electronics Packaging Technology Conference - EPTC, 2/12/2015, p.1-4