Browsing by Author "Perry, Dan"
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Publication Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances
Proceedings paper2010, IEEE International Electron Devices Meeting - IEDM, 6/12/2010, p.26-29Publication Design issues and cosiderations for low-cost 3D TSV IC technology
Proceedings paper2010, IEEE International Solid-State Circuits Conference - ISSCC, 8/02/2010, p.148-149Publication Impact of thinning and packaging on a deep sub-micron CMOS product
; Yang, YuOral presentation2009, Design, Automation & Test in Europe Conference -DATE : Workshop on 3D Integration (W5)Publication Impact of thinning and through silicon via proximity on high-k / metal gate first CMOS performance
Proceedings paper2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.109-110Publication Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design
Proceedings paper2010, 23rd IEEE International Conference on Microelectronic Test Structures - ICMTS, 22/03/2010, p.140-144Publication Test structures for characterization of through silicon vias
Proceedings paper2010, 23rd IEEE International Conference on Microelectronic Test Structures - ICMTS, 22/03/2010, p.130-134