Browsing by Author "Schwarzenbach, Walter"
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Publication 3D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability
; ; ; ; ; Journal article2018-11, IEEE Transactions on Electron Devices, (65) 11, p.5165-5171Publication 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
; ; ; ; ; Proceedings paper2018, IEEE Symposium on VLSI Technology, 18/06/2018, p.69-70Publication Enabling UTBB Strained SOI Platform for Co-integration of Logic and RF: Implant-Induced Strain Relaxation and Comb-like Device Architecture
Proceedings paper2020, IEEE Symposium on VLSI Technology and Circuits, JUN 15-19, 2020Publication Low temperature junctionless device stacking enabled by leading edge
Meeting abstract2019-04, 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 22/04/2019, p.1-2Publication Recent progress in sequential 3D device stacking: low temperature reliable top tier junction-less devices on 300mm wafers
Proceedings paper2019, Extended Abstracts of the International Conference on Solid State Devices and Materials - SSDM, 2/09/2019, p.589-590