Browsing by Author "Verbree, Jouke"
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Publication 3D DfT architecture for pre-bond and post-bond testing
Proceedings paper2010-11, IEEE International 3D Systems Integration Conference - 3DIC, 16/11/2010, p.1Publication A DfT architecture for 3D-SICs based on a standardizable die wrapper
Journal article2012-02, Journal of Electronic Testing - Theory and Applications, (28) 1, p.73-92Publication A standardizable 3D DfT architecture
Oral presentation2010, IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits - 3D-TESTPublication A structured and scalable test access architecture for TSV-based 3D stacked ICs
Proceedings paper2010-04, 28th IEEE VLSI Test Symposium - VTS, 19/04/2010, p.269-274Publication An IEEE Std 1500-based 3D design-for-test architecture
Proceedings paper2010-11, IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits - 3D-TEST, 4/11/2010Publication Cost-effectiveness of wafer-to-wafer 3D chip stacking with matching pre-tested wafers
Oral presentation2010, 3D Integration Workshop at DATE 2010Publication On maximizing the compound yield for 3D wafer-to-wafer stacked ICs
Proceedings paper2010-10, IEEE International Test Conference - ITC, 31/10/2010, p.1-10Publication On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking
Proceedings paper2010, 15th IEEE European Test Symposium - ETS, 24/05/2010, p.36-41Publication Test-architecture optimization and test scheduling for TSV-based 3D stacked ICs
Journal article2011-11, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (30) 11, p.1705-1718Publication Test-architecture optimization for TSV-based 3D stacked ICs
Proceedings paper2010, IEEE European Test Symposium - ETS, 24/05/2010, p.24-29