Browsing by author "Marinissen, Erik Jan"

3D chip stacking: the sky is the limit

Marinissen, Erik Jan (2012-05)

3D design-for-test architecture

Marinissen, Erik Jan; Konijnenburg, Mario; Verbree, Jouke; Chi, Chun-Chuan; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias; Shibin, Konstantin; Keller, Brion; Chickermane, Vivek; Goel, Sandeep K. (2019-03)

3D DfT architecture for pre-bond and post-bond testing

Marinissen, Erik Jan; Chi, Chun-Chuan; Verbree, Jouke; Konijnenburg, Mario (2010-11)

3D IC stacking: Do-It-Yourself short course

Marinissen, Erik Jan (2017-08)

3D IC: Do-It-Yourself (Short Course)

Marinissen, Erik Jan (2016-05)

3D Integration: Circuit design, test and reliability challenges

Minas, Nikolaos; De Wolf, Ingrid; Marinissen, Erik Jan; Stucchi, Michele; Oprins, Herman; Mercha, Abdelkarim; Van der Plas, Geert; Velenis, Dimitrios; Marchal, Pol (2010)

3D-COSTAR for 2.5D and 3D stacked IC cost optimization

Taouil, Mottaqiallah; Hamdioui, Said; Marinissen, Erik Jan (2014-12)

3D-COSTAR: A cost model for 3D stacked ICs

Taouil, Mottaqiallah; Hamdioui, Said; Marinissen, Erik Jan; Bhawmik, Sudipta (2013)

3D-COSTAR: A cost model for 3D-SICs

Taouil, Mottaqiallah; Hamdioui, Said; Marinissen, Erik Jan; Bhawmik, Sudipta (2012-12)

3D-COSTAR: A cost model for 3D-SICs

Taouil, Mottaqiallah; Hamdioui, Said; Marinissen, Erik Jan; Bhawmik, Sudipta (2012-11)

3D-COSTAR: A tool for 2.5D/3D test flow optimization

Taouil, Mottaqiallah; Hamdioui, Said; Marinissen, Erik Jan (2015-10)

3D-SIC test challenges and solutions

Marinissen, Erik Jan (2013)

3D-Test: No Longer a Bottleneck!

Marinissen, Erik Jan (2019-03)

A 3D-DfT demonstrator

Marinissen, Erik Jan; De Wachter, Bart; O'Loughlin, Stephen; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias (2014-05)

A 3D-DfT demonstrator

Marinissen, Erik Jan; De Wachter, Bart; O'Loughlin, Stephen; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias (2014-06)

A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability

Cao, Xugang; Jiao, Hailong; Marinissen, Erik Jan (2022)

A DfT architecture and tool flow for 3D-SICs with test data compression, embedded cores, and multiple towers

Papameletis, Christos; Keller, Brion; Chickermane, Vivek; Hamdioui, Said; Marinissen, Erik Jan (2015)

A DfT architecture for 3D-SICs based on a standardizable die wrapper

Marinissen, Erik Jan; Chi, Chun-Chuan; Konijnenburg, Mario; Verbree, Jouke (2012-02)

A full-automatic test system for characterizing wide-I/O micro-bump probe cards

Marinissen, Erik Jan; Fodor, Ferenc; De Wachter, Bart; Kiesewetter, Joerg; Hill, Eric; Smith, Ken (2017-06)

A fully automatic electro-optical test system enabling the development of a silicon photonic technology platform

De Coster, Jeroen; Magdziak, Rafal; De Heyn, Peter; Marinissen, Erik Jan; Pantouvaki, Marianna; Van Campenhout, Joris; Absil, Philippe; Rishavy, Dan; Frankel, Joe; Kekahuna, Kainoa; Negishi, Kazuki; Simmons, Mike; Christenson, Eric (2019-06)