Browsing by author "Marinissen, Erik Jan"
Now showing items 21-40 of 202
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A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards
Marinissen, Erik Jan; Fodor, Ferenc; De Wachter, Bart; Kiesewetter, Joerg; Hill, Eric; Smith, Ken (2017-09) -
A new DfT standard on the horizon: IEEE Std P1838 for 3D test access
Marinissen, Erik Jan; McLaurin, Teresa (2018-05) -
A standardizable 3D DfT architecture
Marinissen, Erik Jan; Chi, Chun-Chuan; Verbree, Jouke; Konijnenburg, Mario (2010) -
A structured and scalable test access architecture for TSV-based 3D stacked ICs
Marinissen, Erik Jan; Verbree, Jouke; Konijnenburg, Mario (2010-04) -
Abort-on-fail test scheduling for modular SOCs without and with preemption
Ingelsson, Urban; Sandeep Kumar, Goel; Larsson, Erik; Marinissen, Erik Jan (2015) -
Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios
Stucchi, Michele; Fodor, Ferenc; Marinissen, Erik Jan (2020) -
Active-lite interposer for 2.5 & 3D integration
Hellings, Geert; Scholz, Mirko; Detalle, Mikael; Velenis, Dimitrios; de Potter de ten Broeck, Muriel; Roda Neve, Cesar; Li, Yunlong; Van Huylenbroeck, Stefaan; Chen, Shih-Hung; Marinissen, Erik Jan; La Manna, Antonio; Van der Plas, Geert; Linten, Dimitri; Beyne, Eric; Thean, Aaron (2015) -
Adapting to adaptive testing
Marinissen, Erik Jan; Singh, Adit; Glotter, Dan; Esposito, Marco; Carulli, John M.; Nahar, Amit; Butler, Kenneth M.; Appello, Davide; Portelli, Chris (2010-03) -
An IEEE Std 1500-based 3D design-for-test architecture
Marinissen, Erik Jan; Chi, Chun-Chuan; Verbree, Jouke; Konijnenburg, Mario (2010-11) -
Application of cell-aware test on an advanced 3nm CMOS standard-cell library
Gao, Zhan; Hu, Min-Chun; Marinissen, Erik Jan; Malagi, Santosh; Swenton, Joe; Huisken, Jos; Goossens, Kees (2019-05) -
Application of cell-aware test on an advanced 3nm CMOS technology library
Gao, Zhan; Hu, Min-Chun; Baert, Rogier; Chehab, Bilal; Malagi, Santosh; Swenton, Joe; Huisken, Jos; Goossens, Kees; Marinissen, Erik Jan (2019-11) -
At-Speed delay testing of inter-die connections of 2.5D- and 3D-SICs
Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-05) -
At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs
Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-05) -
At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs
Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-05) -
At-speed inter-die interconnect test in 2.5D- and 3D-SICs
Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-10) -
At-speed testing of inter-die connections of 3D-SICs in the presence of shore logic
Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-11) -
Automated design-for-test for 2.5D and 3D SICs
Marinissen, Erik Jan; Konijnenburg, Mario; Deutsch, Sergej; Keller, Brion; Chickermane, Vivek; Mukherjee, Subhasish; Goel, Sandeep K. (2011-09) -
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers
Papameletis, Christos; Keller, Brion; Chickermane, Vivek; Marinissen, Erik Jan; Hamdioui, Said (2013) -
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers
Papameletis, Christos; Keller, Brion; Chickermane, Vivek; Marinissen, Erik Jan; Hamdioui, Said (2013-05) -
Automated probe mark analysis
Rong, Yu-Rong; Wu, Cheng-Wen; Fodor, Ferenc; Marinissen, Erik Jan (2018-06)