Browsing by author "Roda Neve, Cesar"
Now showing items 1-13 of 13
-
A simple and efficient RF technique for the TSV characterization
Sun, Xiao; Roda Neve, Cesar; Van Huylenbroeck, Stefaan; Van der Plas, Geert; Beyne, Eric (2017) -
A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring
Araga, Yuuki; Miura, Ranto; Nagata, Makoto; Roda Neve, Cesar; De Vos, Joeri; Van der Plas, Geert; Beyne, Eric (2014) -
Active-lite interposer for 2.5 & 3D integration
Hellings, Geert; Scholz, Mirko; Detalle, Mikael; Velenis, Dimitrios; de Potter de ten Broeck, Muriel; Roda Neve, Cesar; Li, Yunlong; Van Huylenbroeck, Stefaan; Chen, Shih-Hung; Marinissen, Erik Jan; La Manna, Antonio; Van der Plas, Geert; Linten, Dimitri; Beyne, Eric; Thean, Aaron (2015) -
Broadband metal-insulator-metal capacitors on silicon interposer for low impedance power distribution network
Ueda, Nao; Roda Neve, Cesar; Detalle, Mikael; Beyne, Eric; Van der Plas, Geert; Nagata, Makoto (2015) -
Decoupling capacitor integration in passive silicon interposer
Detalle, Mikael; Roda Neve, Cesar; Nolmans, Philip; Miller, Andy; La Manna, Antonio; Van der Plas, Geert; Beyer, Gerald; Beyne, Eric (2015) -
ESD protection design in active interposer for 2.5 and 3D systems-in-package
Scholz, Mirko; Hellings, Geert; Chen, Shih-Hung; Linten, Dimitri; Detalle, Mikael; Roda Neve, Cesar; Shibkov, Andrei; La Manna, Antonio; Van der Plas, Geert; Beyne, Eric (2015-09) -
High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer
Roda Neve, Cesar; Detalle, Mikael; Nolmans, Philip; Li, Yunlong; De Vos, Joeri; Van der Plas, Geert; Beyer, Gerald; Beyne, Eric (2016) -
Investigation of chip-to-chip interconnections for memory-logic communication on 3D interposer technology
Roda Neve, Cesar; Ryckaert, Julien; Van der Plas, Geert; Detalle, Mikael; Beyne, Eric; Pantano, Nicolas; Verhelst, Marian (2014) -
Modeling the effect of charges in the back side passivation layer on through silicon via (TSV) capacitance after wafer thinning
Rack, Martin; Stucchi, Michele; Sun, Xiao; Roda Neve, Cesar; Van der Plas, Geert; Beyne, Eric; Absil, Philippe; Raskin, J-P (2015) -
Noise coupling between TSVs and active devices: planar nMOSFETs vs. nFinFETs
Sun, Xiao; Rouhi Najaf Abadi, Alireza; Guo, Wei; Bel Ali, K.; Rack, M.; Roda Neve, Cesar; Choi, M.; Moroz, V.; De Wolf, Ingrid; Raskin, J.P.; Van der Plas, Geert; Beyne, Eric; Absil, Philippe (2015) -
Semi-additive Cu-Polymer RDL process for interposers applications
Duval, Fabrice; Detalle, Mikael; Sun, Xiao; Beyne, Eric; Roda Neve, Cesar; Velenis, Dimitrios (2014) -
Technology optimization for high bandwidth density applications on 3D interposer
Pantano, Nicolas; Roda Neve, Cesar; Van der Plas, Geert; Detalle, Mikael; Verhelst, Marian; Heyns, Marc; Beyne, Eric (2016) -
Through silicon via to FinFET noise coupling in 3-D integrated circuits
Rouhi Najaf Abadi, Alireza; Guo, Wei; Sun, Xiao; Ben Ali, K.; Raskin, J.P; Rack, M.; Roda Neve, Cesar; Choi, M.; Moroz, V.; Van der Plas, Geert; De Wolf, Ingrid; Beyne, Eric; Absil, Philippe (2015)