Browsing by author "Verbree, Jouke"
Now showing items 1-11 of 11
-
3D design-for-test architecture
Marinissen, Erik Jan; Konijnenburg, Mario; Verbree, Jouke; Chi, Chun-Chuan; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias; Shibin, Konstantin; Keller, Brion; Chickermane, Vivek; Goel, Sandeep K. (2019-03) -
3D DfT architecture for pre-bond and post-bond testing
Marinissen, Erik Jan; Chi, Chun-Chuan; Verbree, Jouke; Konijnenburg, Mario (2010-11) -
A DfT architecture for 3D-SICs based on a standardizable die wrapper
Marinissen, Erik Jan; Chi, Chun-Chuan; Konijnenburg, Mario; Verbree, Jouke (2012-02) -
A standardizable 3D DfT architecture
Marinissen, Erik Jan; Chi, Chun-Chuan; Verbree, Jouke; Konijnenburg, Mario (2010) -
A structured and scalable test access architecture for TSV-based 3D stacked ICs
Marinissen, Erik Jan; Verbree, Jouke; Konijnenburg, Mario (2010-04) -
An IEEE Std 1500-based 3D design-for-test architecture
Marinissen, Erik Jan; Chi, Chun-Chuan; Verbree, Jouke; Konijnenburg, Mario (2010-11) -
Cost-effectiveness of wafer-to-wafer 3D chip stacking with matching pre-tested wafers
Verbree, Jouke; Marinissen, Erik Jan; Roussel, Philippe; Velenis, Dimitrios (2010) -
On maximizing the compound yield for 3D wafer-to-wafer stacked ICs
Taouil, Mottaqiallah; Hamdioui, Said; Verbree, Jouke; Marinissen, Erik Jan (2010-10) -
On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking
Verbree, Jouke; Marinissen, Erik Jan; Roussel, Philippe; Velenis, Dimitrios (2010) -
Test-architecture optimization and test scheduling for TSV-based 3D stacked ICs
Noia, Brandon; Chakrabarty, Krishnendu; Goel, Sandeep K.; Marinissen, Erik Jan; Verbree, Jouke (2011-11) -
Test-architecture optimization for TSV-based 3D stacked ICs
Noia, Brandon; Goel, Sandeep Kumar; Chakrabarty, Krishnendu; Marinissen, Erik Jan; Verbree, Jouke (2010)