Browsing by author "Yang, Yu"
Now showing items 1-11 of 11
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Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances
Mercha, Abdelkarim; Van der Plas, Geert; Moroz, V.; De Wolf, Ingrid; Asimakopoulos, Panagiotis; Minas, Nikolaos; Domae, Shinichi; Perry, Dan; Choi, M.; Redolfi, Augusto; Okoro, Chukwudi; Yang, Yu; Van Olmen, Jan; Thangaraju, Sarasvathi; Sabuncuoglu Tezcan, Deniz; Soussan, Philippe; Cho, Jong Hoon; Yakovlev, A.; Marchal, Pol; Travaly, Youssef; Beyne, Eric; Biesemans, Serge; Swinnen, Bart (2010) -
Detection of failure sites by focused ion beam and nano-probing in the interconnect of three-dimensional stacked circuit structures
Yang, Yu; Bender, Hugo; Arstila, Kai; Swinnen, Bart; Verlinden, Bert; De Wolf, Ingrid (2008) -
Extraction of the appropriate material property for realistic modeling of through-silicon-vias using μ-raman spectroscopy
Okoro, Chukwudi; Yang, Yu; Vandevelde, Bart; Swinnen, Bart; Vandepitte, Dirk; Verlinden, Bert; De Wolf, Ingrid (2008) -
Impact of thinning and packaging on a deep sub-micron CMOS product
Perry, Dan; Ray, Urmi; Gu, Sam; Nakamoto, Mark; Sy, Wing; Wang, Kevin; Ruythooren, Wouter; Yang, Yu; De Wolf, Ingrid; Cotrin Teixeira, Ricardo; Gonzalez, Mario; Simons, Veerle; Berry, Christopher J.; Lee, KiWook; Burggraf, Jürgen; Pargfrieder, Stefan (2009) -
Impact of thinning and through silicon via proximity on high-k / metal gate first CMOS performance
Mercha, Abdelkarim; Redolfi, Augusto; Stucchi, Michele; Minas, Nikolaos; Van Olmen, Jan; Thangaraju, Sarasvathi; Velenis, Dimitrios; Domae, Shinichi; Yang, Yu; Katti, Guruprasad; Labie, Riet; Okoro, Chukwudi; Zhao, Ming; Asimakopoulos, Panagiotis; De Wolf, Ingrid; Chiarella, Thomas; Schram, Tom; Rohr, Erika; Van Ammel, Annemie; Jourdain, Anne; Ruythooren, Wouter; Armini, Silvia; Radisic, Alex; Philipsen, Harold; Heylen, Nancy; Kostermans, Maarten; Jaenen, Patrick; Sleeckx, Erik; Sabuncuoglu Tezcan, Deniz; Debusschere, Ingrid; Soussan, Philippe; Perry, Dan; Van der Plas, Geert; Cho, Jong Hoon; Marchal, Pol; Travaly, Youssef; Beyne, Eric; Biesemans, Serge; Swinnen, Bart (2010) -
Process induced sub-surface damage in mechanically ground silicon wafers
Yang, Yu; De Munck, Koen; Cotrin Teixeira, Ricardo; Swinnen, Bart; Verlinden, Bert; De Wolf, Ingrid (2008-07) -
Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures
Yang, Yu; Labie, Riet; Ling, Fangzhou; Zhao, Chao; Radisic, Alex; Van Olmen, Jan; Travaly, Youssef; Verlinden, Bert; De Wolf, Ingrid (2010) -
Statistical analysis of the influence of thinning processes on the strength of silicon
Yang, Yu; Cotrin Teixeira, Ricardo; Roussel, Philippe; Swinnen, Bart; Verlinden, Bert; De Wolf, Ingrid (2009) -
Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design
Minas, Nikolaos; Van der Plas, Geert; Oprins, Herman; Yang, Yu; Okoro, Chukwudi; Mercha, Abdelkarim; Torregiani, Cristina; Perry, Dan; Marchal, Pol; Rakowski, Michal; Cherman, Vladimir (2010) -
The impact of back-side Cu contamination on 3D stacking architecture
Yang, Yu; Labie, Riet; Richard, Olivier; Bender, Hugo; Zhao, Chao; Verlinden, Bert; De Wolf, Ingrid (2010)