Browsing by author "Machillot, Jerome"
Now showing items 1-7 of 7
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3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors
Eyben, Pierre; Ritzenthaler, Romain; De Keersgieter, An; Chiarella, Thomas; Veloso, Anabela; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Machillot, Jerome; Kim, Myungsun; Miyashita, Toshihiko; Yoshida, Naomi; Bender, Hugo; Richard, Olivier; Celano, Umberto; Paredis, Kristof; Wouters, Lennaert; Mitard, Jerome; Horiguchi, Naoto (2019) -
CVD Mn-based self-formed barrier for advanced interconnect technology
Siew, Yong Kong; Jourdan, Nicolas; Barbarin, Yohan; Machillot, Jerome; Demuynck, Steven; Croes, Kristof; Tseng, J.; Ai, Hua; Tang, Jing; Naik, M.; Wang, P.; Narasimhan, M.; Abraham, M.; Cockburn, Andrew; Boemmels, Juergen; Tokei, Zsolt (2013) -
CVD-Mn(Nx) as copper diffusion barrier for advanced interconnect technologies
Jourdan, Nicolas; Machillot, Jerome; Barbarin, Yohan; Siew, Yong Kong; Ai, Hua; Cockburn, Andrew; Nguyen, Mai Phuong; Van Elshocht, Sven; Boemmels, Juergen; Lakshmanan, A.; Ma, Paul; Narasimhan, Murali; Tokei, Zsolt (2013) -
Scaled, novel effective workfunction metal gate stacks for advanced Low-VT, gate-all-around vertically stacked nanosheet FETs with reduced vertical distance between sheets
Veloso, Anabela; Simoen, Eddy; Oliveira, Alberto; Vaisman Chasin, Adrian; Chen, S.-C.; Lin, Y.; Miyashita, T.; Kim, M.; Jang, Doyoung; Ritzenthaler, Romain; Zhou, Daisy; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Kenis, Karine; Sebaai, Farid; Mannaert, Geert; Devriendt, Katia; Hopf, Toby; Versluijs, Janko; Richard, Olivier; Machillot, Jerome; Yoshida, Naomi; Horiguchi, Naoto (2019) -
Si/SiGe superlattice I/O finFETs in a vertically-stacked gate-all-around horizontal nanowire technology
Hellings, Geert; Mertens, Hans; Subirats, Alexandre; Simoen, Eddy; Schram, Tom; Ragnarsson, Lars-Ake; Simicic, Marko; Chen, Shih-Hung; Parvais, Bertrand; Boudier, Dimitri; Cretu, Bogdan; Machillot, Jerome; Pena, Vanessa; Sun, S.; Yoshida, N.; Kim, N.; Mocuta, Anda; Linten, Dimitri; Horiguchi, Naoto (2018) -
Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization
Ritzenthaler, Romain; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Vaisman Chasin, Adrian; Kenis, Karine; Devriendt, Katia; Mannaert, Geert; Dekkers, Harold; Dangol, Anish; Lin, Yongjin; Sun, Shiyu; Chen, Zhebo; Kim, Myungsun; Chen, ShiChung; Machillot, Jerome; Mitard, Jerome; Yoshida, Naomi; Kim, Namsung; Mocuta, Dan; Horiguchi, Naoto (2018) -
Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration
Mertens, Hans; Ritzenthaler, Romain; Pena, Vanessa; Santoro, Gaetano; Kenis, Karine; Schulze, Andreas; Dentoni Litta, Eugenio; Chew, Soon Aik; Devriendt, Katia; Chiarella, Thomas; Demuynck, Steven; Yakimets, Dmitry; Jang, Doyoung; Spessot, Alessio; Eneman, Geert; Dangol, Anish; Lagrain, Pieter; Bender, Hugo; Sun, Shiyu; Korolik, Michael; Kioussis, D.; Kim, Myungsun; Bu, Kyung-Ho; Chen, Shih Chung; Cogorno, Matt; Devrajan, J.; Machillot, Jerome; Yoshida, Naomi; Kim, Namsung; Barla, Kathy; Mocuta, Dan; Horiguchi, Naoto (2017)