Browsing by author "Weijtmans, J.W."
Now showing items 1-5 of 5
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Analysis of the pre-epi bake conditions on the defect creation in recessed Si1-xGex S/D junctions
Bargallo Gonzalez, Mireia; Thomas, Nicole; Simoen, Eddy; Verheyen, Peter; Hikavyy, Andriy; Leys, Frederik; Okuno, Yasutoshi; Vissouvanadin Soubaretty, Bertrand; Van Daele, Benny; Geenen, Luc; Loo, Roger; Claeys, Cor; Machkaoutsan, Vladimir; Tomasini, P.; Thomas, S.G.; Lu, J.P.; Weijtmans, J.W.; Wise, R. (2007) -
Factors influencing the leakage current in embedded SiGe source/drain junctions
Simoen, Eddy; Bargallo Gonzalez, Mireia; Vissouvanadin Soubaretty, Bertrand; Chowdhury, Mohammad Kamruzzaman; Verheyen, Peter; Hikavyy, Andriy; Bender, Hugo; Loo, Roger; Claeys, Cor; Machkaoutsan, Vladimir; Tomasini, P.; Thomas, S.; Lu, J.P.; Weijtmans, J.W.; Wise, R. (2008) -
Influence of the highly-doped drain implantation and the window size on defect creation in p/n Si1-xGex source/drain junctions
Chowdhury, Mohammad Kamruzzaman; Vissouvanadin Soubaretty, Bertrand; Bargallo Gonzalez, Mireia; Bhouri, Nada; Verheyen, Peter; Hikavyy, Andriy; Richard, Olivier; Geypen, Jef; Bender, Hugo; Loo, Roger; Claeys, Cor; Simoen, Eddy; Machkaoutsan, Vladimir; Tomasini, P.; Thomas, S.G.; Lu, J.P.; Weijtmans, J.W.; Wise, R. (2008) -
Relaxation induced excess leakage current in recessed Si1-xGex source/drain junctions
Bargallo Gonzalez, Mireia; Chowdhury, Mohammad Kamruzzaman; Bhouri, Nada; Verheyen, Peter; Leys, Frederik; Richard, Olivier; Loo, Roger; Claeys, Cor; Simoen, Eddy; Machkaoutsan, Vladimir; Tomasini, P.; Thomas, S.G.; Lu, J.P.; Weijtmans, J.W.; Wise, R. (2007) -
SiGe recessed source-drain (RSD) stressors for PMOS: effect of device integration flow and increased Ge content on electrical performance
Machkaoutsan, Vladimir; Verheyen, Peter; Tomasini, P.; Eneman, Geert; Loo, Roger; Absil, Philippe; Thomas, S.G.; Lu, Jiong Ping; Weijtmans, J.W.; Wise, R. (2007)