Browsing by author "Van Aerde, Steven"
Now showing items 1-10 of 10
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A 10 μm thick poly-SiGe gyroscope processed above 0.35 μm CMOS
Scheurle, A.; Fuchs, T.; Kehr, K.; Leinenbach, C.; Kronmueller, S.; Arias, A.; Ceballos, J.; Lagos, M.A.; Mora, J.-M.; Munoz, J.M.; Ragel, A.; Ramos, J.; Van Aerde, Steven; Spengler, J.; Mehta, Anshu; Verbist, Agnes; Du Bois, Bert; Witvrouw, Ann (2007-01) -
An ultra-thin hybrid floating gate concept for sub-20nm NAND flash technologies
Wellekens, Dirk; Blomme, Pieter; Rosmeulen, Maarten; Schram, Tom; Cacciato, Antonio; Van Aerde, Steven; Debusschere, Ingrid; Van Houdt, Jan (2011) -
Analysis of performance/variability trade-off in Macaroni-type 3-D NAND Memory
Congedo, Gabriele; Arreghini, Antonio; Liu, Lifang; Capogreco, Elena; Lisoni, Judit; Huet, Karim; Toque-Tresonne, Ines; Van Aerde, Steven; Toledano Luque, Maria; Tan, Chi Lim; Van den Bosch, Geert; Van Houdt, Jan (2014) -
Highly scaled vertical cylindrical SONOS cell with bi-layer poly-silicon channel for 3D NAND flash memory
Van den Bosch, Geert; Kar, Gouri Sankar; Blomme, Pieter; Arreghini, Antonio; Cacciato, Antonio; Breuil, Laurent; De Keersgieter, An; Paraschiv, Vasile; Vrancken, Christa; Douhard, Bastien; Richard, Olivier; Van Aerde, Steven; Debusschere, Ingrid; Van Houdt, Jan (2011) -
Novel bi-layer poly-silicon channel vertical flash cell for ultrahigh density 3D sonos nand technology
Kar, Gouri Sankar; Van den Bosch, Geert; Cacciato, Antonio; Blomme, Pieter; Arreghini, Antonio; Breuil, Laurent; De Keersgieter, An; Paraschiv, Vasile; Vrancken, Christa; Douhard, Bastien; Richard, Olivier; Debusschere, Ingrid; Van Houdt, Jan; Van Aerde, Steven; Tang, Baojun (2011) -
Novel dual layer floating gate structure as enabler of fully planar flash memory
Blomme, Pieter; Rosmeulen, Maarten; Cacciato, Antonio; Kostermans, Maarten; Vrancken, Christa; Van Aerde, Steven; Schram, Tom; Debusschere, Ingrid; Jurczak, Gosia; Van Houdt, Jan (2010) -
Processing of MEMS gyroscopes on top of CMOS ICs
Witvrouw, Ann; Mehta, Anshu; Verbist, Agnes; Du Bois, Bert; Van Aerde, Steven; Ramos-Martos, J.; Ceballos, J.; Ragel, A.; Mora, J.M.; Lagos, M.A.; Arias, A.; Hinojosa, J.M.; Spengler, J.; Leinenbach, C.; Fuchs, T.; Kronmüller, S. (2005-02) -
Scaling of floating gate electrode for sub-40nm flash technologies
De Vos, Joeri; Wellekens, Dirk; Debusschere, Ingrid; Van Houdt, Jan; Van Aerde, Steven; Fischer, Pamela; Zagwijn, Peter (2008) -
SIGEM, low temperature deposition of poly-SiGe MEMs structures on standard CMOS circuits
Ramos-Martos, Juan; Ceballos-Caceres, Joaquin; Ragel-Morales, Antonio; Mora=-Gutierrez, Jose Miguel; Arias-Drake, Alberto; Lagos-Florido, Miguel-ANgel; Munoz-Hinojosa, Jose Maria; Mehta, Anshu; Verbist, Agnes; Du Bois, Bert; Kehr, Kersten; Leinenbach, Christina; Van Aerde, Steven; Spengler, Jorg; Witvrouw, Ann (2005) -
Vertical polysilicon pinch-off FET for 3D memory technology: feasibility and electrical performance
Congedo, Gabriele; Toledano Luque, Maria; Arreghini, Antonio; Kar, Gouri Sankar; Tang, Baojun; Degraeve, Robin; Van Aerde, Steven; Kim, Woosik; Van den Bosch, Geert; Van Houdt, Jan (2013)