Browsing by author "Na, Myung Hee"
Now showing items 1-16 of 16
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3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes
Chen, Rongmei; Weckx, Pieter; Salahuddin, Shairfe Muhammad; Kim, Soon-Wook; Sisto, Giuliano; Van der Plas, Geert; Stucchi, Michele; Baert, Rogier; Debacker, Peter; Na, Myung Hee; Ryckaert, Julien; Milojevic, Dragomir; Beyne, Eric (2020) -
A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in -Memory Analog Matrix -Vector-Multiplier for DNN Acceleration
Papistas, Ioannis; Cosemans, Stefan; Rooseleer, Bram; Doevenspeck, Jonas; Na, Myung Hee; Mallik, Arindam; Debacker, Peter; Verkest, Diederik (2021) -
Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond
Gupta, Anshul; Varela Pedreira, Olalla; Tao, Zheng; Mertens, Hans; Radisic, Dunja; Jourdan, Nicolas; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Chehab, Bilal; Jang, Doyoung; Hellings, Geert; Sebaai, Farid; Lorant, Christophe; Teugels, Lieve; Peter, Antony; Chan, BT; Schleicher, Filip; Demonie, Ingrid; Marien, Philippe; Sepulveda Marquez, Alfonso; Richard, Olivier; Nagesh, Nishanth; Lesniewska, Alicja; Lazzarino, Frederic; Ryckaert, Julien; Morin, Pierre; Altamirano Sanchez, Efrain; Murdoch, Gayle; Boemmels, Juergen; Demuynck, Steven; Na, Myung Hee; Tokei, Zsolt; Biesemans, Serge; Dentoni Litta, Eugenio; Horiguchi, Naoto (2020) -
Buried power SRAM DTCO and system-level benchmarking in N3
Salahuddin, Shairfe Muhammad; Perumkunnil, Manu; Dentoni Litta, Eugenio; Gupta, Anshul; Weckx, Pieter; Ryckaert, Julien; Na, Myung Hee; Spessot, Alessio (2020) -
Design-Technology Co-Optimization of Sequential and Monolithic CFET as enabler of technology node beyond 2nm
Chehab, Bilal; Ryckaert, Julien; Schuddinck, Pieter; Weckx, Pieter; Horiguchi, Naoto; Mirabelli, Gioele; Spessot, Alessio; Na, Myung Hee (2021) -
Design-Technology Space Exploration For Energy Efficient AiMC-based Inference Acceleration
Bhattacharjee, Debjyoti; Laubeuf, Nathan; Cosemans, Stefan; Papistas, Ioannis; Mallik, Arindam; Debacker, Peter; Na, Myung Hee; Verkest, Diederik (2021) -
Disruptive Technology Elements, and Rapid and Accurate Block-Level Performance Evaluation for 3nm and Beyond
Na, Myung Hee; Jang, Doyoung; Baert, Rogier; Sarkar, Satadru; Patli, Sudhir; Zografos, Odysseas; Chehab, Bilal; Spessot, Alessio; Sisto, Giuliano; Schuddinck, Pieter; Mertens, Hans; Oniki, Yusuke; Hellings, Geert; Dentoni Litta, Eugenio; Ryckaert, Julien; Horiguchi, Naoto (2021) -
Enabling sub-5nm CMOS technology scaling thinner and taller!
Ryckaert, Julien; Na, Myung Hee; Weckx, Pieter; Jang, Doyoung; Schuddinck, Pieter; Chehab, Bilal; Patli, Sudhir; Sarkar, Satadru; Zografos, Odysseas; Baert, Rogier; Verkest, Diederik (2019) -
Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips
Samavedam, Sri; Ryckaert, Julien; Beyne, Eric; Ronse, Kurt; Horiguchi, Naoto; Tokei, Zsolt; Radu, Iuliana; Garcia Bardon, Marie; Na, Myung Hee; Spessot, Alessio; Biesemans, Serge (2020) -
IGZO-based compute cell for analog in-memory computing - DTCO analysis to enable ultralow-power AI at edge
Saito, Daisuke; Doevenspeck, Jonas; Cosemans, Stefan; Oh, Hyungrock; Perumkunnil, Manu; Papistas, Ioannis; Belmonte, Attilio; Rassoul, Nouredine; Delhougne, Romain; Kar, Gouri Sankar; Debacker, Peter; Mallik, Arindam; Verkest, Diederik; Na, Myung Hee (2020) -
Inflection points in interconnect research and trends for 2nm and beyond in order to solve the RC bottleneck
Tokei, Zsolt; Vega Gonzalez, Victor; Murdoch, Gayle; O'Toole, Martin; Croes, Kristof; Baert, Rogier; van der Veen, Marleen; Adelmann, Christoph; Soulie, Jean-Philippe; Boemmels, Juergen; Wilson, Chris; Park, Seongho; Sankaran, Kiroubanand; Pourtois, Geoffrey; Swerts, Johan; Paolillo, Sara; Decoster, Stefan; Mao, Ming; Lazzarino, Frederic; Versluijs, Janko; Blanco, Victor; Ercken, Monique; Kesters, Els; Le, Quoc Toan; Holsteyns, Frank; Heylen, Nancy; Teugels, Lieve; Devriendt, Katia; Struyf, Herbert; Morin, Pierre; Jourdan, Nicolas; Van Elshocht, Sven; Ciofi, Ivan; Gupta, Anshul; Zahedmanesh, Houman; Vanstreels, Kris; Na, Myung Hee (2020) -
Introducing 2D-FETs in Device Scaling Roadmap using DTCO
Ahmed, Zubair; Afzalian, Aryan; Schram, Tom; Jang, Doyoung; Verreck, Devin; Smets, Quentin; Schuddinck, Pieter; Chehab, Bilal; Sutar, Surajit; Arutchelvan, Goutham; Soussou, Assawer; Asselberghs, Inge; Spessot, Alessio; Radu, Iuliana; Parvais, Bertrand; Ryckaert, Julien; Na, Myung Hee (2020) -
Monte Carlo comparison of n-type and p-type nanosheets with FinFETs: Effect of the number of sheets
Bufler, Fabian; Jang, Doyoung; Hellings, Geert; Eneman, Geert; Matagne, Philippe; Spessot, Alessio; Na, Myung Hee (2020) -
Progression of logic device and DTCO to enable advance scaling
Sarkar, Satadru; Chehab, Bilal; Ryckaert, Julien; Na, Myung Hee; Spessot, Alessio (2020) -
Thermal stress-aware CMOS-SRAM partitioning in sequential 3-D technology
Salahuddin, Shairfe Muhammad; Dentoni Litta, Eugenio; Gupta, Anshul; Ritzenthaler, Romain; Schaekers, Marc; Everaert, Jean-Luc; Yu, Hao; Vandooren, Anne; Ryckaert, Julien; Na, Myung Hee; Spessot, Alessio (2020) -
Towards extreme scaling of logic standard cells using Forksheet devices
Weckx, Pieter; Ryckaert, Julien; Jang, Doyoung; Chehab, Bilal; Hellings, Geert; Mertens, Hans; Dentoni Litta, Eugenio; Spessot, Alessio; Horiguchi, Naoto; Na, Myung Hee (2020)