Standard cell architectures for N2 node: transition from FinFET to NanoSheet and to ForkSheet device

Abstract

N2 node is introduced at 42nm poly pitch (CPP), 16 metal pitch (MP) by using 5 tracks (5T) cell height, single fin, and buried power rail (BPR). Due to the extreme cell height reduction, the patterning of the middle of line (MOL) become challenging. In this paper, two contact patterning schemes, staggered and aligned are presented and evaluated in terms of their impact on electrical performance on FinFET and Nanosheet. Simulations show that both options meet the performance target for N2. However, scaling at these dimensions also challenges the p-n separation between devices in a logic cell, which results in area penalty in complex cells. A novel device is introduced at N2 node, Forksheet, which shows higher performance and better area scaling at standard cell level compared to FinFET and NanoSheet.