Browsing by author "Jang, Doyoung"
Now showing items 1-20 of 58
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5nm: has the time for a device change come?
Raghavan, Praveen; Garcia Bardon, Marie; Schuddinck, Pieter; Jang, Doyoung; Yakimets, Dmitry; Baert, Rogier; Debacker, Peter; Verkest, Diederik; Thean, Aaron (2016) -
A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node
Gupta, Mohit; Weckx, Pieter; Schuddinck, Pieter; Jang, Doyoung; Chehab, Bilal; Cosemans, Stefan; Ryckaert, Julien; Dehaene, Wim (2021) -
An in-depth study of high-performing strained germanium nanaowires pFETs
Mitard, Jerome; Jang, Doyoung; Eneman, Geert; Arimura, Hiroaki; Parvais, Bertrand; Richard, Olivier; Van Marcke, Patricia; Witters, Liesbeth; Capogreco, Elena; Bender, Hugo; Ritzenthaler, Romain; Mertens, Hans; Hikavyy, Andriy; Loo, Roger; Dekkers, Harold; Sebaai, Farid; Horiguchi, Naoto; Mocuta, Anda; Collaert, Nadine (2018) -
BTI reliability from planar to FinFET nodes: Will the next node be more or less reliable?
Kukner, Halil; Weckx, Pieter; Raghavan, Praveen; Kaczer, Ben; Jang, Doyoung; Catthoor, Francky; Van der Perre, Liesbet; Lauwereins, Rudy; Groeseneken, Guido (2014) -
Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond
Gupta, Anshul; Varela Pedreira, Olalla; Tao, Zheng; Mertens, Hans; Radisic, Dunja; Jourdan, Nicolas; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Chehab, Bilal; Jang, Doyoung; Hellings, Geert; Sebaai, Farid; Lorant, Christophe; Teugels, Lieve; Peter, Antony; Chan, BT; Schleicher, Filip; Demonie, Ingrid; Marien, Philippe; Sepulveda Marquez, Alfonso; Richard, Olivier; Nagesh, Nishanth; Lesniewska, Alicja; Lazzarino, Frederic; Ryckaert, Julien; Morin, Pierre; Altamirano Sanchez, Efrain; Murdoch, Gayle; Boemmels, Juergen; Demuynck, Steven; Na, Myung Hee; Tokei, Zsolt; Biesemans, Serge; Dentoni Litta, Eugenio; Horiguchi, Naoto (2020) -
Comparison of NBTI aging on adder architectures and ring oscillators in the downscaled technologies
Kosemura, Daisuke; Weckx, Pieter; Morrison, Sebastien; Franco, Jacopo; Toledano Luque, Maria; Cho, Moon Ju; Raghavan, Praveen; Kaczer, Ben; Jang, Doyoung; Miyaguchi, Kenichi; Garcia Bardon, Marie; Catthoor, Francky; Van der Perre, Liesbet; Lauwereins, Rudy; Groeseneken, Guido (2015) -
Comparison of temperature dependent carrier transport in FinFET and gate-all-Around nanowire FET
Kim, Soohyun; Kim, Jungchun; Jang, Doyoung; Ritzenthaler, Romain; Parvais, Bertrand; Mitard, Jerome; Mertens, Hans; Chiarella, Thomas; Horiguchi, Naoto; Lee, Jae Woo (2020) -
Dedicated technology threshold voltage tuning for 6T SRAM beyond N7
Gupta, Mohit; Weckx, Pieter; Cosemans, Stefan; Schuddinck, Pieter; Baert, Rogier; Jang, Doyoung; Sherazi, Yasser; Raghavan, Praveen; Spessot, Alessio; Mocuta, Anda; Dehaene, Wim (2017) -
Design technology co-optimization for N10
Ryckaert, Julien; Raghavan, Praveen; Baert, Rogier; Garcia Bardon, Marie; Dusa, Mircea; Mallik, Arindam; Sakhare, Sushil; Vandewalle, Boris; Wambacq, Piet; Chava, Bharani; Croes, Kris; Dehan, Morin; Jang, Doyoung; Leray, Philippe; Liu, Tsung-Te; Miyaguchi, Kenichi; Parvais, Bertrand; Schuddinck, Pieter; Weemaes, Philippe; Mercha, Abdelkarim; Boemmels, Juergen; Horiguchi, Naoto; McIntyre, Greg; Thean, Aaron; Tokei, Zsolt; Cheng, Shaunee; Verkest, Diederik; Steegen, An (2014) -
Device challenges for logic scaling for sub-5 nm node
Jang, Doyoung; Garcia Bardon, Marie; Yakimets, Dmitry; Schuddinck, Pieter; Ragnarsson, Lars-Ake; Sharan, Neha; Parvais, Bertrand; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda (2018) -
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7
Gupta, Mohit; Weckx, Pieter; Cosemans, Stefan; Schuddinck, Pieter; Baert, Rogier; Yakimets, Dmitry; Jang, Doyoung; Sherazi, Yasser; Raghavan, Praveen; Spessot, Alessio; Mocuta, Anda; Dehaene, Wim (2017) -
Device exploration of nanosheet transistors for sub-7nm technology node
Jang, Doyoung; Yakimets, Dmitry; Eneman, Geert; Schuddinck, Pieter; Garcia Bardon, Marie; Raghavan, Praveen; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda (2017) -
Device Scaling roadmap and its implications for Logic and Analog platform
Spessot, Alessio; Parvais, Bertrand; Rawat, Amita; Miyaguchi, Kenichi; Weckx, Pieter; Jang, Doyoung; Ryckaert, Julien (2020) -
Device-, circuit- & block-level evaluation of CFET in a 4 track library
Schuddinck, Pieter; Zografos, Odysseas; Weckx, Pieter; Matagne, Philippe; Sarkar, Satadru; Sherazi, Yasser; Baert, Rogier; Jang, Doyoung; Yakimets, Dmitry; Gupta, Anshul; Parvais, Bertrand; Ryckaert, Julien; Verkest, Diederik; Mocuta, Anda (2019) -
Dimensioning for power and performance under 10nm: The limits of FinFETs scaling
Garcia Bardon, Marie; Schuddinck, Pieter; Raghavan, Praveen; Jang, Doyoung; Yakimets, Dmitry; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron (2015) -
Disruptive Technology Elements, and Rapid and Accurate Block-Level Performance Evaluation for 3nm and Beyond
Na, Myung Hee; Jang, Doyoung; Baert, Rogier; Sarkar, Satadru; Patli, Sudhir; Zografos, Odysseas; Chehab, Bilal; Spessot, Alessio; Sisto, Giuliano; Schuddinck, Pieter; Mertens, Hans; Oniki, Yusuke; Hellings, Geert; Dentoni Litta, Eugenio; Ryckaert, Julien; Horiguchi, Naoto (2021) -
DTCO including Sustainability: Power-Performance-Area-Cost-Environmental score (PPACE) Analysis for Logic Technologies
Garcia Bardon, Marie; Wuytens, Pieter; Ragnarsson, Lars-Ake; Mirabelli, Gioele; Jang, Doyoung; Willems, Geert; Mallik, Arindam; Spessot, Alessio; Ryckaert, Julien; Parvais, Bertrand (2020) -
Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster
Veloso, Anabela; Jourdain, Anne; Hiblot, Gaspard; Schleicher, Filip; D'have, Koen; Sebaai, Farid; Radisic, Dunja; Loo, Roger; Hopf, Toby; De Keersgieter, An; Arimura, Hiroaki; Eneman, Geert; Favia, Paola; Geypen, Jef; Arutchelvan, Goutham; Vaisman Chasin, Adrian; Jang, Doyoung; Nyns, Laura; Rosseel, Erik; Hikavyy, Andriy; Mannaert, Geert; Chan, BT; Devriendt, Katia; Demuynck, Steven; Van der Plas, Geert; Ryckaert, Julien; Beyer, Gerald; Dentoni Litta, Eugenio; Beyne, Eric; Horiguchi, Naoto (2021) -
Enabling sub-5nm CMOS technology scaling thinner and taller!
Ryckaert, Julien; Na, Myung Hee; Weckx, Pieter; Jang, Doyoung; Schuddinck, Pieter; Chehab, Bilal; Patli, Sudhir; Sarkar, Satadru; Zografos, Odysseas; Baert, Rogier; Verkest, Diederik (2019) -
EUV lithography and its enablement of future generations of semiconductor devices
Seong, Nak; Yeon-Hwa, Lim; Chang-Nam, Ahn; Wei-Min, Gao; Jang, Doyoung; Rawat, Amita (2020)