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Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect
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Authors
Pei, Zhenlin
;
Mayahinia, Mahta
;
Liu, Hsiao-Hsuan
;
Tahoori, Mehdi
;
Catthoor, Francky
;
Tokei, Zsolt
;
Pan, Chenyun
DOI
10.1145/3583781.3590311
EISBN
979-8-4007-0125-2
ISSN
na
Conference
33rd Great Lakes Symposium on VLSI (GLSVLSI)
Journal
not applicable
Title
Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect
Publication type
Proceedings paper
Embargo date
2023-07-30
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Date
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3
20.500.12860/42394.3
*
2023-11-30T08:07:57Z
validation by library/open access desk
2
20.500.12860/42394.2
2023-08-29T07:44:08Z
validation by imec author
1
20.500.12860/42394
2023-08-24T17:41:50Z
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