Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures

Abstract

Electron-spin qubits in silicon are one of the most promising platforms for implementing large-scale quantum computing. In this platform, a qubit, i.e., the basic unit of quantum information, is associated with the spin of a single electron confined in a region of silicon called a quantum dot. Electron-spin qubit devices must be operated at the cryogenic temperature of 40mK in a 3He/ 4 He dilution refrigerator. This requirement results in long cool-down (“soak”) times and increased costs, which slow down the technology development. Our research aims at developing a high-volume, room-temperature screening technique to assess quantum dots variability and select suitable candidates for mK measurements. In this paper, we present transistor measurement data of quantum dots across a 300mm wafer at temperatures ranging from 300K down to 225K. We analyze the statistical distributions of transistor metrics to detect outliers across temperatures, and hence to prevent wasting measurement time and resources at mK on known bad devices. From the collected data, we conclude that among the metrics analyzed, the threshold voltage appears to be the preferred metric for an effective pre-screening of silicon quantum dots.