Browsing by Author "Beyne, Eric"
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Publication 10 and 7 mu m Pitch Thermo-compression Solder Joint, Using A Novel Solder Pillar And Metal Spacer Process
Proceedings paper2020, 70th IEEE Electronic Components and Technology Conference (ECTC), JUN 03-30, 2020, p.617-622Publication 20 μm pitch Cu-to-Cu flip-chip interconnects through Cu nanoparticles sintering
Proceedings paper2024, IEEE 74th Electronic Components and Technology Conference (ECTC), MAY 28-31, 2024, p.1891-1895Publication 2D vs 3D integration: Architecture-technology co-design for future mobile MPSoC platforms
Proceedings paper2014, IEEE International Interconnect Technology Conference - IITC, 20/05/2014, p.381-384Publication 2x2 and 4x4 arrays of annular slot antennas in MCM-D technology fed by coplanar CPW networks
Journal article1999, IEE Proceedings - Microwaves, Antennas and Propagation, (146) 5, p.335-338Publication 3-D technology assessment: path-finding the technology/design sweet-spot
Journal article2009, Proceedings of the IEEE, (97) 1, p.96-107Publication 300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications
Meeting abstract2010-11, IEEE International 3D System Integration Conference - 3DIC, 16/11/2010Publication 3D chip package interaction thermo-mechanical challenges: proximity effects of through silicon vias and μ-bumps
Proceedings paper2012, IEEE International Conference on IC Design and technology - ICICDT, 30/05/2012Publication 3D Embedding and interconnection of ultra thin (<20um) silicon dies
Proceedings paper2007, 9th Electronics Packaging Technology Conference - EPTC, 10/12/2007, p.222-226Publication 3D heterogeneous integration techniques for wireless devices
Oral presentation2010, RFIC Symposium Workshop M: RF Packaging Solutions for Wireless Communication PlatformsPublication 3D Heterogeneous Package Integration of Air/Magnetic Core Inductor: 89%-Efficiency Buck Converter with Backside Power Delivery Network
Proceedings paper2020, IEEE Symposium on VLSI Technology and Circuits, JUN 15-19, 2020Publication 3D heterogeneous system integration: Application driver for 3D technology development
Proceedings paper2011, 48th ACM/EDAC/IEEE Design Automation Conference - DAC, 5/06/2011, p.213Publication 3D IC assembly using thermal compression bonding and wafer-level underfill – strategies for quality improvement and throughput enhancement
Proceedings paper2016, IEEE 18th Electronic Packaging Technology Conference - EPTC, 30/11/2016, p.791-796Publication 3D integration - definitions, status and roadmap
Proceedings paper2014, 18th IEEE Workshop on Signal and Power Integrity - SPI, 11/05/2014Publication 3D integration challenges and progress: from TSV to stacked die technologies
Oral presentation2011, IEEE-CPMT Orange County Chapter Seminar "3D Integrated Circuits: Technologies Enabling the Revolution"Publication 3D integration challenges for fine pitch back side micro-bumping on ZoneBOND™ wafers
Proceedings paper2012, 4th Electronics System Integration Technologies Conference - ESTC, 17/09/2012