Browsing by Author "Chakrabarty, Krishnendu"
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Publication Die-wrapper optimization for 3D stacked ICs
Oral presentation2010, IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits - 3D-TESTPublication Optimization methods for post-bond die-internal/external testing in 3D stacked ICs
Proceedings paper2010-10, IEEE International Test Conference - ITC, 31/10/2010, p.1-10Publication Optimization methods for post-bond testing of 3D stacked ICs
Journal article2012-02, Journal of Electronic Testing - Theory and Applications, (28) 1, p.103-120Publication Perspectives on Emerging Computation-in-Memory Paradigms
Proceedings paper2021, Design, Automation and Test in Europe Conference and Exhibition (DATE), FEB 01-05, 2021, p.1925-1934Publication Robust optimization of test-access architectures under realistic scenarios
Journal article2015-11, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), (34) 11, p.1873-1884Publication Test-architecture optimization and test scheduling for TSV-based 3D stacked ICs
Journal article2011-11, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (30) 11, p.1705-1718Publication Test-architecture optimization for TSV-based 3D stacked ICs
Proceedings paper2010, IEEE European Test Symposium - ETS, 24/05/2010, p.24-29Publication Testing of SOCs with hierarchical cores: common fallacies, test-access optimization, and test scheduling
Journal article2009, IEEE Transactions on Computers, (58) 3, p.409-423Publication Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs
Proceedings paper2013-09, IEEE International Test Conference - ITC, 10/09/2013, p.7.1