Browsing by Author "Croon, Jeroen"
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Publication A 0.35μm SiGe BiCMOS process featuring a 80 GHz Fmax HBT and integrated high-Q RF passive components
Proceedings paper2000, Proceedings Bipolar/BiCMOS Circuits and Technology Meeting - BCTM, 24/09/2000, p.106-109Publication A comparison of extraction techniques for threshold voltage mismatch
Proceedings paper2002, International Conference on Microelectronic Test Structures, 8/04/2002, p.235-240Publication A general model for MOS transistor matching
Proceedings paper1999, ESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference; 13-15 September 1999; Leuven, Belgium., p.464-467Publication A simple and accurate deep submicron mismatch model
Proceedings paper2000, Proceedings of the 30th European Solid-State Device Research Conference - ESSDERC, 11/09/2000, p.356-359Publication A simple characterization method for MOS transistor matching in deep submicron technologies
Proceedings paper2001, Proceedings IEEE 2001 International Conference on Microelectronic Test Structures;, p.213-218Publication A yield-aware modeling methodology for nano-scaled SRAM designs
Proceedings paper2005, International Conference on Integrated Circuit Design & Technology, 9/05/2005, p.33-36Publication An easy-to-use mismatch model for the MOS transistor
Journal article2002, IEEE J. Solid-State Circuits, (37) 8, p.1056-1064Publication CMOS device optimisation for mixed-signal technologies
Publication Experimental analysis of a Ge-HfO2-TaN gate stack with a large amount of interface states
Proceedings paper2005-04, Proceedings of the International Conference on Microelectronic Test Structures, 4/04/2005, p.191-196Publication Experimental analysis of a Ge-HfO2-TaN gate stack with a large amount of interface states
Oral presentation2004, Semiconductor Interface Specialists Conference - SISCPublication Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield
Proceedings paper2003, 33rd European Solid-State Devices Research Conference - ESSDERC, 16/09/2003, p.227-230Publication Freeze-out effects on the characteristics of deep submicron Si nMOSFETSs in the 77 K to 300 K range
Proceedings paper1997, Proceedings of the 4th Symposium on Low Temperature Electronics and High Temperature Superconductivity, 4/05/1997, p.187-198Publication Full spectral analysis of line edge roughness
Proceedings paper2005, Metrology, Inspection, and Process Control for Microlithography XIX, 28/02/2005, p.499-509Publication Ge deep sub-micron pFETs with etched TaN metal gate on a High-K dielectric, fabricated in a 200mm silicon prototyping line
Proceedings paper2004, Proceedings of the 34th European Solid-State Device Research Conference - ESSDERC, 21/09/2004, p.189-192Publication Impact of LER and CDU on device performance
Proceedings paper2005, Yield Management Solutions Seminar, 15/08/2005Publication Influence of doping profile and halo implantation on the threshold voltage mismatch of a 0.13μm CMOS technology
Proceedings paper2002, ESSDERC - 32nd European Solid-State Device Research Conference, 24/09/2002, p.579-582Publication Line edge roughness: characterization, modeling and impact on device behavior
Proceedings paper2002, IEDM Technical Digest, 9/12/2002, p.307-310Publication Physical modeling and prediction of the matching properties of MOSFETs
Proceedings paper2004, Proceedings of the 34th European Solid-State Device Research Conference - ESSDERC, 20/09/2004, p.193-196