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Browsing by Author "Givens, M."

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    Demonstration of an InGaAs gate stack with sufficient PBTI reliability by thermal budget optimization, nitridation, high-k material choice, and interface dipole

    Franco, Jacopo  
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    Vais, Abhitosh  
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    Sioncke, Sonja
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    Putcha, Vamsi  
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    Kaczer, Ben  
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    Shie, Bo-Shiuan
    Proceedings paper
    2016, IEEE Symposium on VLSI Technology, 13/06/2016, p.42-43
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    Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices

    Arimura, Hiroaki  
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    Ragnarsson, Lars-Ake  
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    Oniki, Yusuke  
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    Franco, Jacopo  
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    Vandooren, Anne  
    Proceedings paper
    2021, IEEE International Electron Devices Meeting (IEDM), DEC 11-16, 2021
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    Gate-all-around InGaAs nanowire FETs with peak transconductance of 2200 μS/μm at 50nm Lg using a replacement fin RMG flow

    Waldron, Niamh  
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    Sioncke, Sonja
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    Franco, Jacopo  
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    Nyns, Laura  
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    Vais, Abhitosh  
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    Zhou, Daisy  
    Proceedings paper
    2015, IEEE International Electron Devices Meeting - IEDM, 7/12/2015, p.799-802
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    High performance La-doped HZO based ferroelectric capacitors by interfacial engineering

    Popovici, Mihaela Ioana  
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    Bizindavyi, Jasper  
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    Favia, Paola  
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    Clima, Sergiu  
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    Alam, Md Nur Kutubul  
    Proceedings paper
    2022, International Electron Devices Meeting (IEDM), DEC 03-07, 2022
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    Low temperature source / drain epitaxy and functional silicides: essentials for ultimate contact scaling

    Porret, Clément  
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    Everaert, Jean-Luc
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    Schaekers, Marc  
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    Ragnarsson, Lars-Ake  
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    Hikavyy, Andriy  
    Proceedings paper
    2022, International Electron Devices Meeting (IEDM), DEC 03-07, 2022
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    Record mobility (μeff ~3100 cm²/V-s) and reliability performance (Vov~0.5V for 10yr operation) of In0.53Ga0.47As MOS devices using improved surface preparation and a novel interfacial layer

    Vais, Abhitosh  
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    Alian, AliReza  
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    Nyns, Laura  
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    Franco, Jacopo  
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    Sioncke, Sonja
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    Putcha, Vamsi  
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    Yu, Hao  
    Proceedings paper
    2016, IEEE Symposium on VLSI Technology, 13/06/2016, p.140-141

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