Browsing by Author "Jansen, Philippe"
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Publication 0.13µm CMOS technology with optimized poly-Si / NO-oxide gate stack
Proceedings paper1999, ULSI Process Integration. Proceedings of the First International Symposium, 17/10/1999, p.193-202Publication A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits
Publication Advanced modeling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies
Proceedings paper2004, Electrical Overstress / Electrostatic Discharge Symposium Proceedings, 19/09/2004, p.2.B.1Publication Analysis of high voltage ESD protection devices under HBM ESD stress
Proceedings paper2008-05, 2nd International ESD Workshop - IEW, 12/05/2008Publication Bonding techniques for single crystal TFT AMLCD's
Proceedings paper1996, Microelectronic Structures and MEMS for Optical Processing II, 14/10/1996, p.194-200Publication CMOS compatible wafer scale adhesive bonding for circuit transfer
Proceedings paper1997, International Conference on Solid-State Sensors and Actuators - Transducers, 16/06/1997, p.629-632Publication Comparison between short channel bulk (silicon) and body-tied partially depleted SOI nMOS for high frequency low voltage analog circuit design
Publication Consistent small-signal and large-signal extraction techniques for heterojunction FET's
Journal article1995, IEEE Trans. Microwave Theory and Techniques, (43) 1, p.87-93Publication Direct measurement of Leff and channel profile in MOSFETs using 2-D carrier profiling techniques
Proceedings paper1998, Technical Digest International Electron Devices Meeting - IEDM, 6/12/1998, p.559-562Publication ESD circuit model based protection network optimisation for extended-voltage NMOS drivers
Journal article2005-10, Micrelectronics Reliability, (45) 9_11, p.1430-1435Publication Extreme voltage and current overshoots in HV snapback devices during HBM ESD stress
Proceedings paper2008-09, 30th EOS/ESD Symposium, 7/09/2008, p.204-210Publication Far-infrared study of an InAs-GaSb quantum well
Journal article1998, Solid State Communications, (105) 8, p.513-515Publication Gate stack optimisation for advanced CMOS process
Proceedings paper1999, ESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference; 13-15 September 1999; Leuven, Belgium., p.412-415Publication HBM parameter extraction and transient safe operating area
Proceedings paper2010-10, 32nd Annual EOS/ESD Symposium, 3/10/2010, p.425-432Publication Impact of processing parameters on leakage current and defect behavior of n+p silicon junction diodes
Journal article1999, J. Electrochem. Soc., (146) 1, p.359-363Publication Impact of processing parameters on leakage current and defect behavior of n+p silicon junction diodes
Proceedings paper1997, Crystalline Defects and Contamination Control: Their Impact and Control in Device Manufacturing II, 31/08/1997, p.228-239Publication Improving the of ESD self-protection capability of Integrated power NLDMOS arrays
Proceedings paper2010, 32nd Annual EOS/ESD Symposium, 3/10/2010, p.293-299Publication Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications
Proceedings paper2008, IEEE Custom Integrated Circuits Conference - CICC, 21/09/2008, p.49-52Publication Investigation of instrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides
Proceedings paper1999, International Electron Devices Meeting. Technical Digest; 5-8 Dec. 1999; Washington, D.C., USA., p.823-826Publication Lithography options for the 32nm half pitch node and beyond
Journal article2009, IEEE Transactions on Circuits and Systems I: Regular Papers, (56) 8, p.1884-1891