Browsing by Author "Machillot, Jerome"
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Publication 3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors
Proceedings paper2019, IEEE International Electron Devices Meeting - IEDM 2019, 7/12/2019, p.238-241Publication CVD Mn-based self-formed barrier for advanced interconnect technology
Proceedings paper2013, IEEE International Interconnect Technology Conference - IITC, 13/06/2013, p.2.3Publication CVD-Mn(Nx) as copper diffusion barrier for advanced interconnect technologies
Meeting abstract2013, 224th ECS Fall Meeting, 27/10/2013, p.2081Publication Scaled, novel effective workfunction metal gate stacks for advanced Low-VT, gate-all-around vertically stacked nanosheet FETs with reduced vertical distance between sheets
Proceedings paper2019, 2019 International Conference on Solid State Devices and Materials (SSDM 2019), 2/09/2019, p.559-560Publication Si/SiGe superlattice I/O finFETs in a vertically-stacked gate-all-around horizontal nanowire technology
Proceedings paper2018, IEEE Symposium on VLSI Technology, 14/06/2018, p.85-86Publication Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization
Proceedings paper2018, IEEE International Electron Devices Meeting - IEDM, 2/12/2018, p.508-511Publication Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration
Proceedings paper2017, IEEE International Electron Devices Meeting - IEDM, 2/12/2017, p.828-831