Browsing by Author "Moroz, Victor"
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Publication A systematic study of trade-offs in engineering a locally strained pMOSFET
Proceedings paper2004, Technical Digest International Electron Devices Meeting - IEDM, 13/12/2004, p.1055-1058Publication An analytical compact model for estimation of stress in multiple through-silicon via configurations
Proceedings paper2011, Design, Automation and Test in Europe Conference - DATE, 14/03/2011, p.505-506Publication Band-to-band tunneling off-state leakage in Ge fins and nanowires: effect of quantum confinement
Proceedings paper2016, 21st International Conference on Simulation of Semiconductor Processes and Process - SISPAD, 06/09/2016, p.27-30Publication Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology
; ; ; Publication Design Technology Co-Optimization for the DRAM Cell Structure With Contact Resistance Variation
Journal article2024, IEEE TRANSACTIONS ON ELECTRON DEVICES, (71) 3, p.1893-1899Publication Exploring the limits of stress-enhanced hole mobility
Journal article2005-09, IEEE Electron Device Letters, (26) 9, p.652-654Publication Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime
Proceedings paper2014, International Electron Devices Meeting - IEDM, 15/12/2014, p.168-171Publication Impact of litho-patterning variations on the electrical performance and variability of advanced interconnects
Proceedings paper2018, 25th Lithography Workshop, 17/06/2018, p.18Publication Impact of recessed S/D SiGe integration parameters on device performance
Proceedings paper2005, Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 15/05/2005, p.515-522Publication Integration of a recessed SiGe Source/Drain into a PMOS transistor
Proceedings paper2005, 5th International SEMI-ECS Semiconductor Technology Conference, 15/03/2005Publication Layout impact on the performance of a locally strained PMOSFET
Proceedings paper2005, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.22-23Publication Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance
Proceedings paper2013, Symposium on VLSI Technology, 11/06/2013, p.T114-T115Publication Modeling of via resistance for advanced technology nodes
; ; ; Journal article2017, IEEE Transactions on Electron Devices, (64) 5, p.2306-2313Publication Special Issue on "New Simulation Methodologies for Next-Generation TCAD Tools" Foreword
Publication The impact of layout on stress-enhanced transistor performance
Proceedings paper2005, Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices - SISPAD, 1/09/2005, p.143-146