Browsing by Author "Myers, James"

3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs

A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes

Accelerating large language model training with in-package optical links for scale-out systems

Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC

Cryo-Computing for Infrastructure Applications: A Technology-to-Microarchitecture Co-optimization Study

Investigation of die-cost scaling scenarios in future technologies

Late Breaking Results: Thermal Feasibility of Backside Integrated LDOs in 2.5D/3D System-in-Package Using Nanosheet Technology

Managing Crosstalk in multi-GHz Front Side Clock for Back Side Power enabled Sub-2nm 2D/3D ICs

Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures

N2 Nanosheet Pathfinding-PDK (P-PDKTM) Including Back-Side PDN

STCO: driving the More than Moore era

System-Technology Co-Optimization for Dense Edge Architectures Using 3-D Integration and Nonvolatile Memory

Thermal Analysis of High-Performance Server SoCs from FinFET to Nanosheet Technologies

Thermal Implications in Scaling High-Performance Server 3D Chiplet-based 2.5D SoC from FinFET to Nanosheet

Thermal Insights into 3D Packaging of a HighPerformance Server SoC in Advanced Nanosheet Technology

Thermal Performance Evaluation of Multi-core SOCs Using Power-Thermal Co-simulation

Toward Fine-Grained Partitioning of Low-Level SRAM Caches for Emerging 3D-IC Designs

Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus