Browsing by Author "Okuno, Yasutoshi"
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Publication Analysis of the pre-epi bake conditions on the defect creation in recessed Si1-xGex S/D junctions
Proceedings paper2007, Analytical and Diagnostic Techniques for Semiconductor Materials, Devices, and Processes 7, 7/10/2007, p.47-53Publication Influence of STI trench fill and dummy design on CMP behavior
Proceedings paper2007, International Conference on Planarization / CMP Technology - ICPT, 25/10/2007, p.99-104Publication Junction anneal sequence optimization for advanced high-k / metal gate CMOS technology
Proceedings paper2009, 9th International Workshop on Junction Technology - IWJT, 11/06/2009Publication Novel process to pattern selectively dual dielectric capping layers using soft-mask only
Proceedings paper2008, Symposium on VLSI Technology Digest of Technical Papers, 17/06/2008, p.44-45Publication Optimized ultra-low thermal budget process flow for advanced high-K / metal gate first CMOS using laser-annealing technology
Proceedings paper2009, Symposium on VLSI Technology, 15/06/2009, p.38-39Publication Strain enhanced Low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay
Proceedings paper2008, Symposium on VLSI Technology Digest of Technical Papers, 17/06/2008, p.130-131Publication Stress memorization technique – fundamental understanding and low-cost integration for advanced CMOS technology using a nonselective process
Journal article2009, IEEE Transactions on Electron Devices, (56) 8, p.1690-1697Publication Thermally-stable high effective work function TaCN thin films for metal gate electrode applications
Journal article2009, Journal of Applied Physics, (105) 5, p.53516