Browsing by Author "Radu, Ionut"
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Publication 3D sequential CMOS top tier devices demonstration using a low temperature Smart Cu (TM) Si layer transfer
Proceedings paper2021, 26th Silicon Nanoelectronics Workshop, JUN 13, 2021, p.47-48Publication 3D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability
; ; ; ; ; Journal article2018-11, IEEE Transactions on Electron Devices, (65) 11, p.5165-5171Publication 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
; ; ; ; ; Proceedings paper2018, IEEE Symposium on VLSI Technology, 18/06/2018, p.69-70Publication Recent progress in sequential 3D device stacking: low temperature reliable top tier junction-less devices on 300mm wafers
Proceedings paper2019, Extended Abstracts of the International Conference on Solid State Devices and Materials - SSDM, 2/09/2019, p.589-590Publication The use of ion implantation of strained silicon on SiO2 for nanoelectronic devices