Browsing by Author "Sakhare, Sushil"

A comparative analysis on the impact of bank contention in STT-MRAM and SRAM based LLCs

A comprehensive benchmark and optimization of 5-nm lateral and vertical GAA 6T-SRAMs

Cross-layer design and analysis of al ow power, high density STT-MRAM for embedded systems

Design technology co-optimization for a robust 10nm solution for logic design and Sram

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM

Design technology co-optimization for N10

Distinctive behavior of perpendicular magnetic tunnel junctions with size comparable to the electrical switching nucleation

Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

Impact of interconnect multiple-patterning variability on SRAMs

JSWof 5.5 MA/cm2 and RA of 5.2- $X $lm2 STT-MRAM technology for LLC application

Layout optimization and trade-off between 193i and EUV-based patterning for SRAM cells to improve performance and process variability at 7nm technology node

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

Simplistic simulation-based device-VT-targeting technique to determine technology high-density LELE-gate-patterned FinFET SRAM in sub-10 nm era

Solving the BEOL compatibility challenge of top-pinned magnetic tunnel junction stacks

SRAM designs for 5nm node and beyond: opportunities and challenges

Switching characteristics of perpendicular magnetic tunnel junction with various sizes

Thermal stability and switching performance metrics of top-pinned STT-MRAM devices with CMOS-compatible dual MgO MTJ stacks

Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

Vertical device architecture for 5nm and beyond: device & circuit implications