Browsing by Author "Thangaraju, Sarasvathi"
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Publication Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances
Proceedings paper2010, IEEE International Electron Devices Meeting - IEDM, 6/12/2010, p.26-29Publication Impact of thinning and through silicon via proximity on high-k / metal gate first CMOS performance
Proceedings paper2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.109-110Publication Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers
Proceedings paper2011-06, IEEE 61st Electronic Components and Technology Conference - ECTC, 31/05/2011, p.1384-1388Publication Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications
Proceedings paper2011, IEEE 61st Electronic Components and Technology Conference - ECTC, 31/05/2011, p.1122-1125Publication On the thermal stability of physically-vapor-deposited diffusion barriers in 3D through-silicon vias during IC processing
Journal article2013, Microelectronic Engineering, 106, p.155-159Publication Plasma enhanced atomic layer deposition of silicon oxide for through silicon via
Publication Relationships between deposition parameters, step coverage, throughput, and electrical properties of PEALD SiO2 insulation liners for HVM TSV application
Publication Technology assessment of through-silicon via by using C-V and C-t Measurements
Journal article2011, IEEE Electron Device Letters, (32) 7, p.946-948Publication Thermal stability of copper through-silicon via barriers during IC processing
Proceedings paper2011, IEEE International Interconnect Technology Conference and Materials for Advanced Metallization - IITC/MAM, 8/05/2012, p.P2.51