Browsing by Author "Van der Plas, Geert"
- Results Per Page
- Sort Options
Publication 10 and 7 mu m Pitch Thermo-compression Solder Joint, Using A Novel Solder Pillar And Metal Spacer Process
Proceedings paper2020, 70th IEEE Electronic Components and Technology Conference (ECTC), JUN 03-30, 2020, p.617-622Publication 3-D Integration from system design perspective
Oral presentation2009, International Symposium on System-on-Chip - SoCPublication 3D chip package interaction thermo-mechanical challenges: proximity effects of through silicon vias and μ-bumps
Proceedings paper2012, IEEE International Conference on IC Design and technology - ICICDT, 30/05/2012Publication 3D Heterogeneous Package Integration of Air/Magnetic Core Inductor: 89%-Efficiency Buck Converter with Backside Power Delivery Network
Proceedings paper2020, IEEE Symposium on VLSI Technology and Circuits, JUN 15-19, 2020Publication 3D heterogeneous system integration: Application driver for 3D technology development
Proceedings paper2011, 48th ACM/EDAC/IEEE Design Automation Conference - DAC, 5/06/2011, p.213Publication 3D Integration: Circuit design, test and reliability challenges
Proceedings paper2010, 16th IEEE International On-Line Testing Symposium - IOLTS, 5/07/2010, p.217Publication 3D SoC integration, beyond 2.5D chiplets
Proceedings paper2021, IEEE International Electron Devices Meeting (IEDM), DEC 11-16, 2021Publication 3D stacking induced mechanical stress effects
Proceedings paper2014, IEEE 64th Electronic Components and Technology Conference - ECTC, 27/05/2014, p.309-315Publication 3D technology roadmap and status
Proceedings paper2011, IEEE International Interconnect Technology Conference and Materials for Advanced Metallization - IITC/MAM, 8/05/2011Publication 3D Wafer-to-Wafer Bonding Thermal Resistance Comparison: Hybrid Cu/dielectric Bonding versus Dielectric via-last Bonding
; ; ; ; Publication 3D-Integration: status, opportunities
; Marchal, PolOral presentation2011, 16th Asia and South Pacific Design Automation Conference - ASP-DACPublication 3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes
Proceedings paper2020, IEEE International Electron Devices Meeting (IEDM), DEC 12-18, 2020Publication 3D-stacked integrated circuits: design consequences, architectural aspects, design methodologies and tools
Oral presentation2009, 9th Architectures and Compilers for Embedded Systems Symposium - ACESPublication 84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor
Journal article2022, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, (30) 5, p.661-665Publication 91.5%-Efficiency fully integrated voltage regulator with 86fF/μm2-high-density 2.5 MIM capacitor
Proceedings paper2021, 2021 Symposium on VLSI Technology, 13/06/2021Publication A 0.65-to-1.4 nJ/burst 3-to-10 GHz UWB all-digital TX in 90 nm CMOS for IEEE 802.15.4a
Journal article2007, IEEE Journal of Solid-State Circuits, (42) 12, p.2860-2869Publication A 0.65-to-1.4nJ/burst 3-to-10GHz UWB digital transmitter in 90nm CMOS for IEEE 802.15.4a
Proceedings paper2007-02, Technical Digest International Solid-State Circuits Conference - ISSCC, 11/02/2007, p.120-121,591Publication A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC sigma-delta modulator in 1.2-V 90-nm CMOS
; Proceedings paper2010, 36th European Solid-State Circuits Conference - ESSCIRC, 13/09/2010, p.418-421Publication A 14 bit 130 MHz CMOS current-steering DAC with adjustable INL
Proceedings paper2004-09, Proceedings of the 30th European Solid-State Circuits Conference - ESSCIRC, 21/09/2004, p.167-170Publication A 150MS/s 133uW 7b ADC in 90nm digital CMOS using a comparator-based asynchronous binary search sub-ADC
; Verbruggen, BobProceedings paper2008-02, IEEE International Solid-State Circuits Conference - ISSCC, 3/02/2008, p.242-243