Browsing by Author "Yamamoto, Kazuhiko"
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Publication 45nm LSTP FET with FUSI gate on PVD-HfO2 with excellent drivability by advanced PDA treatment
Journal article2005, Microelectronic Engineering, 80, p.7-10Publication High-k dielectrics integration prospects
Proceedings paper2005, ULSI Process Integration IV, 15/05/2005, p.169-192Publication Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS
Proceedings paper2005-04, Proceedings IEEE VLSI-TSA International Symposium on VLSI Technology, 25/04/2005, p.99-100Publication Prospect of Hf-based gate dielectric by PVD with FUSI gate for LSTP application
Publication PVD-HfSiON gate dielectrics with Ni-FUSI electrode for 65nm LSTP application
Journal article2005-06, Microelectronic Engineering, 80, p.198-201Publication The importance of moisture control for EOT scaling of Hf-based dielectrics
Journal article2009, Journal of the Electrochemical Society, (156) 6, p.H416-H423